| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 3368 { ISD::CTLZ, MVT::v8i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3369 { ISD::CTLZ, MVT::v16i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3370 { ISD::CTLZ, MVT::v32i16, { 18, 27, 23, 27 } }, in getIntrinsicInstrCost()
3371 { ISD::CTLZ, MVT::v64i8, { 3, 16, 9, 11 } }, in getIntrinsicInstrCost()
3372 { ISD::CTLZ, MVT::v4i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3373 { ISD::CTLZ, MVT::v8i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3374 { ISD::CTLZ, MVT::v16i16, { 8, 19, 11, 13 } }, in getIntrinsicInstrCost()
3375 { ISD::CTLZ, MVT::v32i8, { 2, 11, 9, 10 } }, in getIntrinsicInstrCost()
3376 { ISD::CTLZ, MVT::v2i64, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
3377 { ISD::CTLZ, MVT::v4i32, { 1, 5, 1, 1 } }, in getIntrinsicInstrCost()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 160 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
234 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARC/ |
| D | ARCExpandPseudos.cpp | 146 case ARC::CTLZ: in runOnMachineFunction()
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| D | ARCISelLowering.cpp | 171 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in ARCTargetLowering()
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| D | ARCInstrInfo.td | 138 def CTLZ : PseudoInstARC<(outs GPR32:$A),
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 702 CTLZ, enumerator
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| D | BasicTTIImpl.h | 2096 ISD = ISD::CTLZ; in getTypeBasedIntrinsicInstrCost()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | ExpandLargeFpConvert.cpp | 354 Function *CTLZ = in expandIToFP() local
369 Value *Call = Builder.CreateCall(CTLZ, {IsSigned ? Sub : IntVal, True}); in expandIToFP()
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| /openbsd/src/gnu/llvm/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSimplifyDemanded.cpp | 667 if (unsigned CTLZ = DemandedMask.countLeadingZeros()) { in SimplifyDemandedUseBits() local
668 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedUseBits()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 106 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
107 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 345 case ISD::CTLZ: in LegalizeOp()
809 case ISD::CTLZ: in Expand()
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| D | SelectionDAGDumper.cpp | 440 case ISD::CTLZ: return "ctlz"; in getOperationName()
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| D | TargetLowering.cpp | 1789 if (unsigned CTLZ = DemandedBits.countLeadingZeros()) { in SimplifyDemandedBits() local
1790 APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); in SimplifyDemandedBits()
4274 N0.getOperand(0).getOpcode() == ISD::CTLZ && in SimplifySetCC()
8370 isOperationLegalOrCustom(ISD::CTLZ, VT)) in expandCTLZ()
8371 return DAG.getNode(ISD::CTLZ, dl, VT, Op); in expandCTLZ()
8377 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); in expandCTLZ() local
8381 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ); in expandCTLZ()
8508 !isOperationLegalOrCustom(ISD::CTLZ, VT) && in expandCTTZ()
8517 !isOperationLegal(ISD::CTLZ, VT)) in expandCTTZ()
8530 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) { in expandCTTZ()
[all …]
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| D | LegalizeIntegerTypes.cpp | 67 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
567 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTLZ, NVT) && in PromoteIntRes_CTLZ()
621 !TLI.isOperationLegal(ISD::CTLZ, NVT)) { in PromoteIntRes_CTTZ()
2427 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 2703 case ISD::CTLZ: in ExpandNode()
4505 case ISD::CTLZ: in PromoteNode()
4527 if (Node->getOpcode() == ISD::CTLZ || in PromoteNode()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 203 setOperationAction(ISD::CTLZ, T, Legal); in initializeHVXLowering()
292 setOperationAction(ISD::CTLZ, T, Custom); in initializeHVXLowering()
1894 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)}); in LowerHvxCttz()
2871 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, InpTy, Abs); in ExpandHvxIntToFp()
3162 case ISD::CTLZ: in LowerHvxOperation()
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| D | HexagonISelLowering.cpp | 1558 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1559 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1631 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE, in HexagonTargetLowering()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 234 setOperationAction(ISD::CTLZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
238 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering()
1444 case ISD::CTLZ: in LowerOperation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 129 setOperationAction(ISD::CTLZ, MVT::i64, Custom); in BPFTargetLowering()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 392 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
417 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
436 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
1275 case ISD::CTLZ: in LowerOperation()
2356 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
2497 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 127 setOperationAction(ISD::CTLZ, MVT::i32, Legal); in LanaiTargetLowering()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 300 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in RISCVTargetLowering()
303 setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand); in RISCVTargetLowering()
612 setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, VT, Expand); in RISCVTargetLowering()
685 {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in RISCVTargetLowering()
917 {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in RISCVTargetLowering()
3615 if (Op.getOpcode() == ISD::CTLZ) in lowerCTLZ_CTTZ_ZERO_UNDEF()
4236 case ISD::CTLZ: in LowerOperation()
7842 case ISD::CTLZ: in ReplaceNodeResults()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 267 setOperationAction(ISD::CTLZ, VT, Legal); in addMVEVectorTypes()
963 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in ARMTargetLowering()
964 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand); in ARMTargetLowering()
1189 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in ARMTargetLowering()
4107 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR); in LowerINTRINSIC_WO_CHAIN()
4127 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi); in LowerINTRINSIC_WO_CHAIN()
4134 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo); in LowerINTRINSIC_WO_CHAIN()
6468 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); in LowerCTTZ() local
6469 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ); in LowerCTTZ()
6493 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); in LowerCTTZ()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 328 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType()
2076 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1713 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1780 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
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