Searched refs:CvtSrc (Results 1 – 3 of 3) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPostLegalizerCombiner.cpp | 283 Register CvtSrc = MatchInfo.CvtVal; in applyCvtF32UByteN() local
287 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
291 B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); in applyCvtF32UByteN()
|
| D | AMDGPUISelLowering.cpp | 3985 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local
3986 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
3989 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
3997 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4001 SDValue CvtSrc = N0.getOperand(0); in performFNegCombine() local
4003 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
4006 CvtSrc.getOperand(0), N0.getOperand(1)); in performFNegCombine()
4013 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 15102 SDValue CvtSrc = N1.getOperand(0); in visitFSUBForFMACombine() local
15103 SDValue N100 = CvtSrc.getOperand(0); in visitFSUBForFMACombine()
15104 SDValue N101 = CvtSrc.getOperand(1); in visitFSUBForFMACombine()
15105 SDValue N102 = CvtSrc.getOperand(2); in visitFSUBForFMACombine()
15108 CvtSrc.getValueType())) { in visitFSUBForFMACombine()
|