| /openbsd/src/gnu/llvm/compiler-rt/lib/builtins/ |
| D | cpu_model.c | 291 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, in detectX86FamilyModel() argument 293 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 in detectX86FamilyModel() 294 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 in detectX86FamilyModel() 298 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 in detectX86FamilyModel() 300 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 in detectX86FamilyModel() 649 unsigned EAX, EBX; in getAvailableFeatures() local 684 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && in getAvailableFeatures() 685 ((EAX & 0x6) == 0x6); in getAvailableFeatures() 693 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); in getAvailableFeatures() 700 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures() [all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86InstrSVM.td | 28 let Uses = [EAX] in 32 let Uses = [EAX] in 40 let Uses = [EAX] in 48 let Uses = [EAX] in 56 let Uses = [EAX, ECX] in
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| D | X86InstrSystem.td | 87 let Defs = [EAX], Uses = [DX] in 97 let Defs = [EAX] in 106 let Uses = [DX, EAX] in 116 let Uses = [EAX] in 426 let Uses = [EAX, ECX, EDX] in 428 let Uses = [EAX, ECX, EDX] in 430 let Defs = [EAX, EDX], Uses = [ECX] in 459 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in 542 let Defs = [EDX, EAX], Uses = [ECX] in 545 let Uses = [EDX, EAX, ECX] in [all …]
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| D | X86InstrTSX.td | 27 let isBranch = 1, isTerminator = 1, Defs = [EAX] in { 34 // Pseudo instruction to fake the definition of EAX on the fallback code path. 35 let isPseudo = 1, Defs = [EAX] in {
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| D | X86FixupGadgets.cpp | 356 case X86::EAX: in getWidestRegForReg() 358 return Is64Bit ? X86::RAX : X86::EAX; in getWidestRegForReg() 419 case X86::EAX: in getEquivalentRegForReg() 448 case X86::EAX: in getEquivalentRegForReg() 469 case X86::EAX: in getEquivalentRegForReg() 493 case X86::EAX: in getEquivalentRegForReg() 502 case X86::EAX: in getEquivalentRegForReg() 504 return X86::EAX; in getEquivalentRegForReg() 614 unsigned OrigReg2 = Is64Bit ? X86::RAX : X86::EAX; in fixupInstruction()
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| D | X86InstrExtension.td | 17 let Defs = [EAX], Uses = [AX] in // EAX = signext(AX) 20 let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX) 29 let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
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| D | X86InstrArithmetic.td | 71 // EAX,EDX = EAX*GR32 72 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in 75 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>, 97 // EAX,EDX = EAX*[mem32] 98 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in 117 // EAX,EDX = EAX*GR32 118 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in 135 // EAX,EDX = EAX*[mem32] 136 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in 289 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in [all …]
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| D | X86DynAllocaExpander.cpp | 226 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() 240 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() 254 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower()
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| D | X86InstrKL.td | 19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in { 22 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
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| D | X86CallingConv.td | 50 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 77 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 227 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 279 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>, 296 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 327 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 409 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 743 CCIfType<[i32], CCAssignToReg<[EAX]>>, 905 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, [all …]
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| D | X86CallingConv.cpp | 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() 242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
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| D | X86InstrSNP.td | 28 let Uses = [EAX] in
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| D | X86SelectionDAGInfo.cpp | 58 X86::ECX, X86::EAX, X86::EDI}; in EmitTargetCodeForMemset() 86 ValReg = X86::EAX; in EmitTargetCodeForMemset()
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| D | X86RegisterInfo.td | 140 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; 165 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 418 (add EAX, ECX, EDX, ESI, EDI, 456 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 458 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 478 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 519 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
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| D | X86InstrInfo.td | 1469 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1476 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1573 let Defs = [EDI], Uses = [EAX,EDI,DF] in 1587 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in 1699 let Defs = [EAX] in 1715 let Defs = [EAX] in 1728 let Uses = [EAX] in 1744 let Uses = [EAX] in 1761 let Defs = [EAX] in 1780 let Uses = [EAX] in [all …]
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| D | X86FrameLowering.cpp | 172 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX || in isEAXLiveIn() 249 unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX); in emitSPUpdate() 309 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate() 720 unsigned Reg = Is64Bit ? X86::RAX : X86::EAX; in emitStackProbeInlineGenericBlock() 779 : X86::EAX; in emitStackProbeInlineGenericLoop() 1148 unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX; in emitStackProbeCall() 1256 : X86::EAX; in BuildStackAlignAND() 1911 .addReg(X86::EAX, RegState::Kill) in emitPrologue() 1926 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) in emitPrologue() 1941 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX), in emitPrologue() [all …]
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Support/Solaris/sys/ |
| D | regset.h | 24 #undef EAX
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| /openbsd/src/gnu/usr.bin/binutils/gdb/ |
| D | i386v4-nat.c | 96 EAX, ECX, EDX, EBX,
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| D | i386v-nat.c | 67 EAX, ECX, EDX, EBX,
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| /openbsd/src/gnu/llvm/compiler-rt/lib/xray/ |
| D | xray_x86_64.cpp | 334 unsigned int EAX, EBX, ECX, EDX; in probeRequiredCPUFeatures() local 339 __asm__ __volatile__("cpuid" : "=a"(EAX), "=b"(EBX), "=c"(ECX), "=d"(EDX) in probeRequiredCPUFeatures()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 196 {codeview::RegisterId::EAX, X86::EAX}, in initLLVMToSEHAndCVRegMapping() 761 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero() 773 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero() 810 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero() 846 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero() 847 return X86::EAX; in getX86SubSuperRegisterOrZero() 882 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
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| D | X86MCTargetDesc.h | 51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
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| /openbsd/src/gnu/usr.bin/binutils/gdb/gdbserver/ |
| D | linux-i386-low.c | 60 EAX * 4, ECX * 4, EDX * 4, EBX * 4,
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| /openbsd/src/gnu/llvm/llvm/lib/DebugInfo/PDB/Native/ |
| D | NativeRawSymbol.cpp | 191 return codeview::RegisterId::EAX; in getLocalBasePointerRegisterId() 247 return codeview::RegisterId::EAX; in getRegisterId()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 134 ENTRY(EAX) \ 152 ENTRY(EAX) \
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