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Searched refs:HW_H_UINT (Results 1 – 25 of 36) sorted by relevance

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/openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/
Dmt-desc.c199 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
352 { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
356 { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
360 { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
364 { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
368 { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
372 { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
376 { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
380 { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
384 { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
[all …]
Dxstormy16-desc.c231 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
406 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
410 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
414 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
418 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
422 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
426 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
434 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
438 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
442 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
[all …]
Dxc16x-desc.c635 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
807 { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
811 { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
815 { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
819 { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
855 { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
859 { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
879 { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
883 { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
887 { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
[all …]
Dfr30-desc.c264 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
434 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
438 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
442 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
446 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
450 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
470 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
474 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
482 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
486 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
[all …]
Diq2000-desc.c225 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
362 { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
366 { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
382 { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
386 { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
390 { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
394 { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
398 { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
402 { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
406 { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
[all …]
Dip2k-desc.c276 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
354 { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
366 { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
370 { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
374 { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
378 { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
382 { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
Dm32r-opinst.c64 { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
396 { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
428 { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
507 { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
568 { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
574 { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
583 { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
590 { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
Dm32r-desc.c240 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
367 { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
371 { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
375 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
379 { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
383 { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
387 { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
Dopenrisc-desc.c196 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
305 { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
317 { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
333 { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
337 { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
Dfrv-desc.c1825 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
2213 { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2221 { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2237 { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2245 { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2249 { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2253 { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2265 { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2269 { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2273 { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
[all …]
Dopenrisc-desc.h202 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dip2k-desc.h205 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
/openbsd/src/gnu/usr.bin/binutils/opcodes/
Dxstormy16-desc.c231 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
406 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
410 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
414 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
418 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
422 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
426 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
434 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
438 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
442 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
[all …]
Dfr30-desc.c264 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
434 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
438 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
442 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
446 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
450 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
470 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
474 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
482 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
486 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
[all …]
Diq2000-desc.c225 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
362 { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
366 { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
382 { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
386 { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
390 { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
394 { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
398 { "f-index", IQ2000_OPERAND_F_INDEX, HW_H_UINT, 8, 9,
402 { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
406 { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
[all …]
Dip2k-desc.c276 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
354 { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
366 { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
370 { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
374 { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
378 { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
382 { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
Dm32r-opinst.c64 { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
396 { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
428 { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
507 { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
568 { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
574 { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
583 { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
590 { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
Dm32r-desc.c240 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
367 { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
371 { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
375 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
379 { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
383 { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
387 { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
Dopenrisc-desc.c196 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
305 { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
317 { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
333 { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
337 { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
Dopenrisc-desc.h186 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dm32r-desc.h167 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dfrv-desc.c1780 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
2159 { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2167 { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2183 { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2191 { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2195 { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2199 { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2211 { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2215 { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2219 { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
[all …]
Dip2k-desc.h189 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dfr30-desc.h191 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dxstormy16-desc.h218 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator

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