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Searched refs:IsRV64 (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVInstrInfoZk.td76 let Predicates = [HasStdExtZknd, IsRV64] in {
81 } // Predicates = [HasStdExtZknd, IsRV64]
83 let Predicates = [HasStdExtZkndOrZkne, IsRV64] in {
87 } // Predicates = [HasStdExtZkndOrZkne, IsRV64]
94 let Predicates = [HasStdExtZkne, IsRV64] in {
97 } // Predicates = [HasStdExtZkne, IsRV64]
115 let Predicates = [HasStdExtZknh, IsRV64] in {
120 } // Predicates = [HasStdExtZknh, IsRV64]
146 let Predicates = [HasStdExtZknd, IsRV64] in {
150 } // Predicates = [HasStdExtZknd, IsRV64]
[all …]
DRISCVInstrInfoM.td49 let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
52 } // Predicates = [HasStdExtMOrZmmul, IsRV64]
54 let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
63 } // Predicates = [HasStdExtM, IsRV64]
84 let Predicates = [HasStdExtMOrZmmul, IsRV64] in
87 let Predicates = [HasStdExtM, IsRV64] in {
107 } // Predicates = [HasStdExtM, IsRV64]
109 let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
116 } // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
DRISCVInstrInfoZb.td329 let Predicates = [HasStdExtZba, IsRV64] in {
340 } // Predicates = [HasStdExtZba, IsRV64]
352 let Predicates = [HasStdExtZbbOrZbkb, IsRV64], IsSignExtendingOpW = 1 in {
360 } // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
403 let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
410 } // Predicates = [HasStdExtZbb, IsRV64]
450 let Predicates = [HasStdExtZbkb, IsRV64], IsSignExtendingOpW = 1 in
459 let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in {
462 } // Predicates = [HasStdExtZbb, IsRV64]
469 let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
[all …]
DRISCVInstrInfoC.td340 let Predicates = [HasStdExtCOrZca, IsRV64] in
374 let Predicates = [HasStdExtCOrZca, IsRV64] in
415 Predicates = [HasStdExtCOrZca, IsRV64] in
477 let Predicates = [HasStdExtCOrZca, IsRV64] in {
525 let Predicates = [HasStdExtCOrZca, IsRV64] in
585 let Predicates = [HasStdExtCOrZca, IsRV64] in
729 let Predicates = [HasStdExtCOrZca, IsRV64] in {
779 let Predicates = [HasStdExtCOrZca, IsRV64] in {
782 } // Predicates = [HasStdExtCOrZca, IsRV64]
799 let Predicates = [HasStdExtCOrZca, IsRV64] in {
[all …]
DRISCVInstrInfoD.td56 def D64Ext : ExtInfo<0, [HasStdExtD, IsRV64]>;
57 def ZdinxExt : ExtInfo<1, [HasStdExtZdinx, IsRV64]>;
187 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
199 let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in
230 let Predicates = [HasStdExtZdinx, IsRV64] in {
238 } // Predicates = [HasStdExtZdinx, IsRV64]
262 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
393 let Predicates = [HasStdExtD, IsRV64] in {
433 } // Predicates = [HasStdExtD, IsRV64]
DRISCVInstrInfoXVentana.td17 let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
31 let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
110 } // Predicates = [IsRV64, HasVendorXVentanaCondOps]
DRISCVInstrInfoZfh.td42 def Zfh64Ext : ExtInfo<0, [HasStdExtZfh, IsRV64]>;
46 def Zhinx64Ext : ExtInfo<1, [HasStdExtZhinx, IsRV64]>;
263 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
390 let Predicates = [HasStdExtZfh, IsRV64] in {
418 } // Predicates = [HasStdExtZfh, IsRV64]
453 let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
469 } // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
DRISCVInstrInfoA.td80 let Predicates = [HasStdExtA, IsRV64] in {
102 } // Predicates = [HasStdExtA, IsRV64]
121 let Predicates = [HasAtomicLdSt, IsRV64] in {
310 let Predicates = [HasStdExtA, IsRV64] in {
378 } // Predicates = [HasStdExtA, IsRV64]
DRISCVInstrInfo.td759 let Predicates = [IsRV64] in {
786 } // Predicates = [IsRV64]
852 let Predicates = [IsRV64, HasStdExtH] in {
895 let Predicates = [IsRV64] in {
899 } // Predicates = [IsRV64]
906 let Predicates = [IsRV64] in {
909 } // Predicates = [IsRV64]
1047 let Predicates = [IsRV64] in {
1063 } // Predicates = [IsRV64]
1591 let Predicates = [IsRV64], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
[all …]
DRISCVFrameLowering.cpp66 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSPrologue() local
71 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue()
116 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); in emitSCSEpilogue() local
121 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue()
DRISCVInstrInfoF.td113 def F64Ext : ExtInfo<0, [HasStdExtF, IsRV64]>;
115 def Zfinx64Ext : ExtInfo<1, [HasStdExtZfinx, IsRV64]>;
514 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
626 let Predicates = [HasStdExtF, IsRV64] in {
660 } // Predicates = [HasStdExtF, IsRV64]
DRISCVInstrInfoV.td1056 let Predicates = [IsRV64, HasVInstructionsI64] in {
1059 } // [IsRV64, HasVInstructionsI64]
1748 let Predicates = [HasVInstructionsI64, IsRV64] in {
1768 } // Predicates = [HasVInstructionsI64, IsRV64]
DRISCVFeatures.td476 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVBaseInfo.cpp42 bool IsRV64 = TT.isArch64Bit(); in computeTargetABI() local
49 } else if (ABIName.startswith("ilp32") && IsRV64) { in computeTargetABI()
53 } else if (ABIName.startswith("lp64") && !IsRV64) { in computeTargetABI()
68 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
112 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
113 unsigned XLen = IsRV64 ? 64 : 32; in parseFeatureBits()
DRISCVMatInt.cpp51 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; in generateInstSeqImpl() local
75 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
81 assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); in generateInstSeqImpl()
372 bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit]; in getIntMatCost() local
375 int PlatRegSize = IsRV64 ? 64 : 32; in getIntMatCost()
DRISCVBaseInfo.h413 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp281 bool IsRV64; member
319 IsRV64 = o.IsRV64; in RISCVOperand()
357 bool isGPRF64AsFPR() const { return isGPR() && IsGPRAsFPR && IsRV64; } in isGPRF64AsFPR()
360 return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - RISCV::X0) & 1); in isGPRPF64AsFPR()
780 bool isRV64() const { return IsRV64; } in isRV64()
837 bool IsRV64) { in createToken()
842 Op->IsRV64 = IsRV64; in createToken()
847 SMLoc E, bool IsRV64, in createReg()
853 Op->IsRV64 = IsRV64; in createReg()
859 SMLoc E, bool IsRV64) { in createImm()
[all …]
/openbsd/src/gnu/llvm/clang/lib/Driver/ToolChains/
DRISCVToolchain.cpp159 bool IsRV64 = ToolChain.getArch() == llvm::Triple::riscv64; in ConstructJob() local
161 if (IsRV64) { in ConstructJob()
DGnu.cpp1759 bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64; in findRISCVMultilibs() local
1762 addMultilibFlag(!IsRV64, "m32", Flags); in findRISCVMultilibs()
1763 addMultilibFlag(IsRV64, "m64", Flags); in findRISCVMultilibs()