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Searched refs:MCII (Results 1 – 25 of 95) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.h48 MCInstrInfo const &MCII; variable
55 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
56 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
87 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
92 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
99 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
103 bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
109 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
117 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
121 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
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DHexagonMCInstrInfo.cpp39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
88 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
92 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
96 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); in addConstExtender()
103 HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII, in bundleInstructions() argument
106 return make_range(Hexagon::PacketIterator(MCII, MCI), in bundleInstructions()
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DHexagonMCChecker.cpp58 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
74 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in initReg()
77 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
104 const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) || in init()
105 HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) && in init()
127 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
169 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && in init()
173 else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) == in init()
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DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
104 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
106 HexagonMCShuffler MCS(Context, ReportErrors, MCII, STI, MCB); in HexagonMCShuffle()
130 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
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DHexagonShuffler.cpp109 HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII, in HexagonCVIResource() argument
115 const unsigned ItinUnits = HexagonMCInstrInfo::getCVIResources(MCII, STI, *id); in HexagonCVIResource()
131 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
132 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
169 MCInstrInfo const &MCII, in HexagonShuffler() argument
171 : Context(Context), BundleFlags(), MCII(MCII), STI(STI), in HexagonShuffler()
184 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
200 const unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); in restrictSlot1AOK()
232 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
373 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
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DHexagonMCShuffler.h32 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
34 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
39 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
41 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
59 MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
64 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
DHexagonMCCodeEmitter.cpp342 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
406 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && in EncodeSingleInstruction()
409 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
418 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
460 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, in getFixupNoBits() argument
462 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits()
463 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
474 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); in getFixupNoBits()
476 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) in getFixupNoBits()
582 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) || in getExprOpValue()
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DHexagonAsmBackend.cpp45 std::unique_ptr <MCInstrInfo> MCII; member in __anon86307cd30111::HexagonAsmBackend
67 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
540 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
543 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
544 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
546 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && in isInstRelaxable()
548 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
550 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
553 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
676 *MCII, CrntHMI, in relaxInstruction()
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DHexagonShuffler.h88 HexagonCVIResource(MCInstrInfo const &MCII,
108 HexagonInstr(MCInstrInfo const &MCII, in HexagonInstr() argument
111 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
165 MCInstrInfo const &MCII; variable
196 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
229 return (*Pred)(MCII, Inst); in HasInstWith()
DHexagonMCCodeEmitter.h36 MCInstrInfo const &MCII; variable
50 : MCT(MCT), MCII(MII) {} in HexagonMCCodeEmitter()
78 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
/openbsd/src/gnu/llvm/llvm/include/llvm/MCA/
DCustomBehaviour.h39 const MCInstrInfo &MCII; variable
42 InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrPostProcess() argument
43 : STI(STI), MCII(MCII) {} in InstrPostProcess()
70 const MCInstrInfo &MCII; variable
74 const MCInstrInfo &MCII) in CustomBehaviour() argument
75 : STI(STI), SrcMgr(SrcMgr), MCII(MCII) {} in CustomBehaviour()
144 const MCInstrInfo &MCII; variable
147 InstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrumentManager() argument
148 : STI(STI), MCII(MCII) {} in InstrumentManager()
169 getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.h21 std::unique_ptr<const MCInstrInfo> const MCII; variable
25 MCInstrInfo const *MCII) in AArch64Disassembler() argument
26 : MCDisassembler(STI, Ctx), MCII(MCII) {} in AArch64Disassembler()
/openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430MCCodeEmitter.cpp37 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
74 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
75 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
202 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter() argument
204 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/MCTargetDesc/
DWebAssemblyMCCodeEmitter.cpp39 const MCInstrInfo &MCII; member in __anon8f48eb170111::WebAssemblyMCCodeEmitter
51 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) : MCII(MCII) {} in WebAssemblyMCCodeEmitter() argument
55 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) { in createWebAssemblyMCCodeEmitter() argument
56 return new WebAssemblyMCCodeEmitter(MCII); in createWebAssemblyMCCodeEmitter()
87 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
/openbsd/src/gnu/llvm/llvm/lib/MC/
DMCSchedule.cpp69 const MCInstrInfo &MCII, in computeInstrLatency() argument
71 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
78 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
112 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
114 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
124 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/openbsd/src/gnu/llvm/llvm/tools/llvm-mca/
Dllvm-mca.cpp406 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in main() local
407 assert(MCII && "Unable to create instruction info!"); in main()
410 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
421 Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MRI)); in main()
436 *MCII); in main()
463 TheTarget->createInstrumentManager(*STI, *MCII)); in main()
468 IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); in main()
478 *MCII, *IM); in main()
508 Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); in main()
531 TheTarget->createInstrPostProcess(*STI, *MCII)); in main()
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/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp33 const MCInstrInfo &MCII; member in __anon421e16210111::R600MCCodeEmitter
37 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
82 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
84 return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo()); in createR600MCCodeEmitter()
90 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
161 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/MCTargetDesc/
DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
108 const MCInstrInfo &MCII; variable
DAVRMCELFStreamer.h26 std::unique_ptr<MCInstrInfo> MCII; variable
34 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
42 MCII(createAVRMCInstrInfo()) {} in AVRMCELFStreamer()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in __anon16f3c4700111::HexagonDisassembler
50 MCInstrInfo const *MCII) in HexagonDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
65 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in fullValue()
200 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, in getInstruction()
469 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
470 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction()
480 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
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/openbsd/src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
DX86AsmBackend.cpp122 std::unique_ptr<const MCInstrInfo> MCII; member in __anon37619e0b0111::X86AsmBackend
141 MCII(T.createMCInstrInfo()) { in X86AsmBackend()
237 const MCInstrInfo &MCII) { in getCondFromBranch() argument
243 const MCInstrDesc &Desc = MCII.get(Opcode); in getCondFromBranch()
251 classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII) { in classifySecondInstInMacroFusion() argument
252 X86::CondCode CC = getCondFromBranch(MI, MCII); in classifySecondInstInMacroFusion()
257 static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII) { in isRIPRelative() argument
259 const MCInstrDesc &Desc = MCII.get(Opcode); in isRIPRelative()
271 static bool isPrefix(const MCInst &MI, const MCInstrInfo &MCII) { in isPrefix() argument
272 return X86II::isPrefix(MCII.get(MI.getOpcode()).TSFlags); in isPrefix()
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/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCTargetDesc.h38 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
66 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
67 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.h44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
45 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
77 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
80 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
/openbsd/src/gnu/llvm/llvm/tools/llvm-mc-assemble-fuzzer/
Dllvm-mc-assemble-fuzzer.cpp111 MCInstrInfo &MCII, MCTargetOptions &MCOptions) { in AssembleInput() argument
118 TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions)); in AssembleInput()
184 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in AssembleOneInput() local
186 *MAI, *MCII, *MRI); in AssembleOneInput()
232 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); in AssembleOneInput()
241 *MCII, MCOptions); in AssembleOneInput()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVMCCodeEmitter.cpp44 MCInstrInfo const &MCII; member in __anonb93aa7890111::RISCVMCCodeEmitter
47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in RISCVMCCodeEmitter() argument
48 : Ctx(ctx), MCII(MCII) {} in RISCVMCCodeEmitter()
90 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, in createRISCVMCCodeEmitter() argument
92 return new RISCVMCCodeEmitter(Ctx, MCII); in createRISCVMCCodeEmitter()
185 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
261 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); in getImmOpValue()

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