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Searched refs:MI1 (Results 1 – 25 of 27) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64MachineScheduler.cpp36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite() argument
39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
46 int StoreSize1 = AArch64InstrInfo::getMemScale(MI1); in mayOverlapWrite()
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
51 ? AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() in mayOverlapWrite()
52 : AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() * StoreSize1; in mayOverlapWrite()
54 const MachineInstr &MI = (Off0 < Off1) ? MI0 : MI1; in mayOverlapWrite()
DAArch64CollectLOH.cpp285 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
312 Info.MI1 = nullptr; in handleUse()
354 OpInfo.MI1 = &MI; in handleMiddleInst()
356 } else if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
359 OpInfo.MI1 = &MI; in handleMiddleInst()
368 if (OpInfo.Type == MCLOH_AdrpAddStr && OpInfo.MI1 == nullptr) { in handleMiddleInst()
371 OpInfo.MI1 = &MI; in handleMiddleInst()
376 OpInfo.MI1 = &MI; in handleMiddleInst()
439 MachineInstr *AddMI = const_cast<MachineInstr *>(Info.MI1); in handleADRP()
447 << '\t' << MI << '\t' << *Info.MI1 << '\t' in handleADRP()
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/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp398 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr() argument
401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
464 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
468 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()
469 (MI1->getOpcode() == Mips::LW_MM) || in ReduceXWtoXWP()
470 (MI1->getOpcode() == Mips::LW16_MM); in ReduceXWtoXWP()
472 if (!CheckXWPInstr(MI1, ReduceToLwp, Entry)) in ReduceXWtoXWP()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
484 bool ConsecutiveForward = ConsecutiveInstr(MI1, MI2); in ReduceXWtoXWP()
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/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp465 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
503 if (MDT.dominates(MI1, MI2)) { in hoistAndMergeSGPRInits()
504 if (!interferes(MI2, MI1)) { in hoistAndMergeSGPRInits()
513 } else if (MDT.dominates(MI2, MI1)) { in hoistAndMergeSGPRInits()
514 if (!interferes(MI1, MI2)) { in hoistAndMergeSGPRInits()
517 << printMBBReference(*MI1->getParent()) << " " << *MI1); in hoistAndMergeSGPRInits()
518 MergedInstrs.insert(MI1); in hoistAndMergeSGPRInits()
524 auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(), in hoistAndMergeSGPRInits()
532 if (!interferes(MI1, I) && !interferes(MI2, I)) { in hoistAndMergeSGPRInits()
535 << printMBBReference(*MI1->getParent()) << " " << *MI1 in hoistAndMergeSGPRInits()
[all …]
DGCNHazardRecognizer.cpp2187 const MachineInstr *MI1; in checkMAIHazards90A() local
2189 auto IsOverlappedMFMAFn = [Reg, &FullReg, &MI1, in checkMAIHazards90A()
2195 MI1 = &MI; in checkMAIHazards90A()
2209 unsigned Opc1 = MI1->getOpcode(); in checkMAIHazards90A()
2221 TSchedModel.computeInstrLatency(MI1) == 2) in checkMAIHazards90A()
2238 if (ST.hasGFX940Insts() && isXDL(ST, *MI) && !isXDL(ST, *MI1)) in checkMAIHazards90A()
2240 switch (TSchedModel.computeInstrLatency(MI1)) { in checkMAIHazards90A()
2243 ? isXDL(ST, *MI1) in checkMAIHazards90A()
2252 NeedWaitStates = isXDL(ST, *MI1) in checkMAIHazards90A()
2258 ? isXDL(ST, *MI1) in checkMAIHazards90A()
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DSIInstrInfo.cpp450 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, in memOpsHaveSameBasePtr() argument
460 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand()) in memOpsHaveSameBasePtr()
463 auto MO1 = *MI1.memoperands_begin(); in memOpsHaveSameBasePtr()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DTargetInstrInfo.cpp427 const MachineInstr &MI1, in produceSameValue() argument
429 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
706 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
709 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
714 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB); in hasReassociableOperands()
726 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
732 Commuted = !areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
735 std::swap(MI1, MI2); in hasReassociableSibling()
745 return areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) && in hasReassociableSibling()
746 (isAssociativeAndCommutative(*MI1) || in hasReassociableSibling()
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DDFAPacketizer.cpp301 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias() argument
304 if (MI1.memoperands_empty() || MI2.memoperands_empty()) in alias()
307 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
DLoadStoreOpt.h49 bool aliasIsKnownForLoadStore(const MachineInstr &MI1, const MachineInstr &MI2,
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp268 MachineInstr &MI1 = *SU.getInstr(); in apply() local
270 bool IsStoreMI1 = MI1.mayStore(); in apply()
271 bool IsLoadMI1 = MI1.mayLoad(); in apply()
272 if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1)) in apply()
DHexagonVLIWPacketizer.cpp966 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements() argument
970 if (getPredicateSense(MI1, HII) == PK_Unknown || in arePredicatesComplements()
975 SUnit *SU = MIToSUnit[&MI1]; in arePredicatesComplements()
1023 unsigned PReg1 = getPredicatedRegister(MI1, HII); in arePredicatesComplements()
1028 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
1029 HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2); in arePredicatesComplements()
DHexagonVLIWPacketizer.h144 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
DHexagonInstrInfo.h406 bool isToBeScheduledASAP(const MachineInstr &MI1,
418 bool addLatencyToSchedule(const MachineInstr &MI1,
DHexagonInstrInfo.cpp2683 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP() argument
2685 if (mayBeCurLoad(MI1)) { in isToBeScheduledASAP()
2687 Register DstReg = MI1.getOperand(0).getReg(); in isToBeScheduledASAP()
2695 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2696 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3031 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule() argument
3033 if (isHVXVec(MI1) && isHVXVec(MI2)) in addLatencyToSchedule()
3034 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DDFAPacketizer.h189 bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
DTargetInstrInfo.h587 const MachineInstr &MI1,
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp276 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
398 int64_t X86OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, in getAddrDispShift() argument
402 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp); in getAddrDispShift()
DX86ISelLowering.h1741 MachineBasicBlock *EmitLoweredCascadedSelect(MachineInstr &MI1,
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp316 MachineInstr &MI1 = *MII; in ExpandFPMLxInstruction()
317 dbgs() << " " << MI1; in ExpandFPMLxInstruction()
DARMBaseInstrInfo.cpp1861 const MachineInstr &MI1, in produceSameValue() argument
1870 if (MI1.getOpcode() != Opcode) in produceSameValue()
1872 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1876 const MachineOperand &MO1 = MI1.getOperand(1); in produceSameValue()
1906 if (MI1.getOpcode() != Opcode) in produceSameValue()
1908 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1912 Register Addr1 = MI1.getOperand(1).getReg(); in produceSameValue()
1929 const MachineOperand &MO1 = MI1.getOperand(i); in produceSameValue()
1936 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
DARMBaseInstrInfo.h239 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DLoadStoreOpt.cpp103 bool GISelAddressing::aliasIsKnownForLoadStore(const MachineInstr &MI1, in aliasIsKnownForLoadStore() argument
107 auto *LdSt1 = dyn_cast<GLoadStore>(&MI1); in aliasIsKnownForLoadStore()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVInstrInfo.h259 bool hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2);
DRISCVInstrInfo.cpp2859 bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) { in hasEqualFRM() argument
2861 RISCV::getNamedOperandIdx(MI1.getOpcode(), RISCV::OpName::frm); in hasEqualFRM()
2866 MachineOperand FrmOp1 = MI1.getOperand(MI1FrmOpIdx); in hasEqualFRM()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp1484 auto MI1 = in expandLSLW4Rd() local
1490 MI1->getOperand(3).setIsDead(); in expandLSLW4Rd()
1570 auto MI1 = in expandLSLW12Rd() local
1576 MI1->getOperand(3).setIsDead(); in expandLSLW12Rd()
1682 auto MI1 = in expandLSRW4Rd() local
1688 MI1->getOperand(3).setIsDead(); in expandLSRW4Rd()

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