Searched refs:MSR (Results 1 – 25 of 40) sorted by relevance
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| /openbsd/src/gnu/llvm/clang/lib/StaticAnalyzer/Checkers/cert/ |
| D | PutenvWithAutoChecker.cpp | 47 const MemSpaceRegion *MSR = ArgV.getAsRegion()->getMemorySpace(); in checkPostCall() local
49 if (!isa<StackSpaceRegion>(MSR)) in checkPostCall()
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| /openbsd/src/sys/dev/pcmcia/ |
| D | if_xereg.h | 107 #define MSR 0xc /* RW - Misc. setup register */ macro
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| D | if_xe.c | 1357 bus_space_write_1(bst, bsh, offset + MSR, in xe_full_reset()
1358 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); in xe_full_reset()
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| /openbsd/src/etc/etc.i386/ |
| D | MAKEDEV.md | 22 __devitem(amdmsr, amdmsr, AMD MSR access device)dnl
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCInstrHTM.td | 91 // value of the MSR Transaction State (TS) bits that exist before the
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| D | P9InstrResources.td | 936 (instregex "M(T|F)MSR(D)?$"),
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| /openbsd/src/gnu/usr.bin/binutils/opcodes/ |
| D | ia64-waw.tbl | 86 MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
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| D | ia64-raw.tbl | 111 MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific
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| D | ia64-ic.tbl | 126 mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr]
191 mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr]
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| D | ChangeLog-0001 | 1808 * arm-opc.h: Use upper case for flasg in MSR and MRS
1810 the MSR instruction.
1813 field_mask of an MSR instruction.
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| /openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/ |
| D | ia64-waw.tbl | 87 MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
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| D | ia64-raw.tbl | 112 MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific
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| D | ChangeLog | 175 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
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| D | ia64-ic.tbl | 126 mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr]
192 mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr]
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| D | ChangeLog-0001 | 1808 * arm-opc.h: Use upper case for flasg in MSR and MRS
1810 the MSR instruction.
1813 field_mask of an MSR instruction.
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64SMEInstrInfo.td | 140 // MSR SVCRSM, #<imm1>
141 // MSR SVCRZA, #<imm1>
142 // MSR SVCRSMZA, #<imm1>
237 (MSR 0xde85, GPR64:$val)>;
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| D | AArch64.td | 670 // Named operands for MRS/MSR/TLBI/...
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| D | AArch64SchedFalkorDetails.td | 1257 def : InstRW<[FalkorWr_1SD_1ST_0cyc], (instrs MSR)>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMScheduleM7.td | 401 // MSR/MRS
402 def : InstRW<[M7NonGeneralPurpose], (instregex "MSR", "MRS")>;
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| D | ARMScheduleR52.td | 343 def : InstRW<[R52WriteLd, R52Read_EX1], (instregex "MSR", "MSRbanked")>;
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| D | ARMScheduleA57.td | 134 "(t2)?MSR(banked|i|_AR|_M)?$")>;
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| D | ARMInstrInfo.td | 5812 // No need to have both system and application versions of MSR (immediate) or
5813 // MSR (register), the encodings are the same and the assembly parser has no way
5818 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5846 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
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| /openbsd/src/gnu/usr.bin/binutils/gdb/ |
| D | rs6000-nat.c | 171 return MSR; in regmap()
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| /openbsd/src/sys/arch/i386/conf/ |
| D | files.i386 | 137 # AMD Geode LX series MSR access
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| D | GENERIC | 38 amdmsr0 at mainbus? # MSR access for AMD Geode LX CPUs with GP
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