Searched refs:MTC0 (Results 1 – 12 of 12) sorted by relevance
| /openbsd/src/sys/arch/mips64/mips64/ |
| D | cp0access.S | 56 MTC0 v0, COP_0_CAUSE_REG # save it
67 MTC0 v0, COP_0_CAUSE_REG # save it
78 MTC0 v0, COP_0_CAUSE_REG # save it
89 MTC0 v0, COP_0_CAUSE_REG # save it
105 MTC0 v1, COP_0_STATUS_REG # enable all interrupts
116 MTC0 v1, COP_0_STATUS_REG # disable all interrupts
132 MTC0 v1, COP_0_STATUS_REG
135 MTC0 v1, COP_0_STATUS_REG
142 MTC0 a0, COP_0_STATUS_REG
165 MTC0 a0, COP_0_CONFIG
[all …]
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| D | exception.S | 184 MTC0 t0, COP_0_STATUS_REG
213 MTC0 t0, COP_0_STATUS_REG
224 MTC0 t0, COP_0_STATUS_REG
233 MTC0 t0, COP_0_STATUS_REG
255 MTC0 t0, COP_0_STATUS_REG # must set exception level bit.
289 MTC0 t0, COP_0_STATUS_REG
298 MTC0 t0, COP_0_STATUS_REG
323 MTC0 t0, COP_0_STATUS_REG
333 MTC0 t0, COP_0_STATUS_REG
343 MTC0 t0, COP_0_STATUS_REG
[all …]
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| D | lcore_float.S | 66 MTC0 t0, COP_0_STATUS_REG
160 MTC0 t1, COP_0_STATUS_REG # Restore the status register.
170 MTC0 t0, COP_0_STATUS_REG
264 MTC0 t1, COP_0_STATUS_REG # Restore the status register.
292 MTC0 t0, COP_0_STATUS_REG
343 MTC0 t1, COP_0_STATUS_REG # Restore the status register.
354 MTC0 t0, COP_0_STATUS_REG
405 MTC0 t1, COP_0_STATUS_REG # Restore the status register.
432 MTC0 v1, COP_0_STATUS_REG
436 MTC0 v1, COP_0_STATUS_REG
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| D | context.S | 121 MTC0 s1, COP_0_STATUS_REG
272 MTC0 v0, COP_0_STATUS_REG
297 MTC0 t0, COP_0_STATUS_REG
301 MTC0 t0, COP_0_STATUS_REG # must set exception level bit.
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| D | lcore_ddb.S | 226 MTC0 v0, COP_0_STATUS_REG
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| /openbsd/src/sys/arch/mips64/include/ |
| D | asm.h | 185 #define MTC0 mtc0 macro
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| D | cpustate.h | 112 MTC0 t1, COP_0_STATUS_REG ;\
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 682 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptPrologueStub()
765 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014) in emitInterruptEpilogueStub()
773 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012) in emitInterruptEpilogueStub()
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| D | MipsScheduleP5600.td | 93 MFC0, MTC0)>;
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| D | MipsScheduleGeneric.td | 450 def : InstRW<[GenericWriteCOP0], (instrs MTC0)>;
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| D | MipsInstrInfo.td | 2455 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>,
2850 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>,
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5845 case Mips::MTC0: in checkTargetMatchPredicate()
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