| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMParallelDSP.cpp | 143 void AddMulPair(MulCandidate *Mul0, MulCandidate *Mul1, in AddMulPair() argument
147 << *Mul1->Root << "\n"); in AddMulPair()
149 Mul1->Paired = true; in AddMulPair()
151 Mul1->Exchange = true; in AddMulPair()
152 MulPairs.push_back(std::make_pair(Mul0, Mul1)); in AddMulPair()
613 const Instruction *Mul1 = PMul1->Root; in CreateParallelPairs() local
614 if (Mul0 == Mul1) in CreateParallelPairs()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 2009 WeightedLeaf Mul1, Mul2; in balanceSubTree() local
2058 if (!Mul1.Value.getNode()) { in balanceSubTree()
2059 Mul1 = WeightedLeaf(Child, Weight, InsertionOrder++); in balanceSubTree()
2121 if (CanFactorize && (willShiftRightEliminate(Mul1.Value, MaxPowerOf2) || in balanceSubTree()
2124 int Weight = Mul1.Weight + Mul2.Weight; in balanceSubTree()
2125 int Height = std::max(NodeHeights[Mul1.Value], NodeHeights[Mul2.Value]) + 1; in balanceSubTree()
2126 SDValue Mul1Factored = factorOutPowerOf2(Mul1.Value, MaxPowerOf2); in balanceSubTree()
2128 SDValue Sum = CurDAG->getNode(ISD::ADD, SDLoc(N), Mul1.Value.getValueType(), in balanceSubTree()
2131 Mul1.Value.getValueType()); in balanceSubTree()
2132 SDValue New = CurDAG->getNode(ISD::SHL, SDLoc(N), Mul1.Value.getValueType(), in balanceSubTree()
[all …]
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 575 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, in isADDADDMUL() argument
600 Mul1 = OtherOp.getOperand(1); in isADDADDMUL()
610 Mul1 = AddOp.getOperand(0).getOperand(1); in isADDADDMUL()
620 Mul1 = AddOp.getOperand(1).getOperand(1); in isADDADDMUL()
1736 SDValue Mul0, Mul1, Addend0, Addend1; in PerformDAGCombine() local
1738 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { in PerformDAGCombine()
1741 Mul1, Addend0, Addend1); in PerformDAGCombine()
1751 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && in PerformDAGCombine()
1753 DAG.MaskedValueIsZero(Mul1, HighMask) && in PerformDAGCombine()
1759 Mul1, DAG.getConstant(0, dl, MVT::i32)); in PerformDAGCombine()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 1543 MachineOperand &Mul1 = Prev.getOperand(1); in combineFPFusedMultiply() local
1556 .addReg(Mul1.getReg(), getKillRegState(Mul1.isKill())) in combineFPFusedMultiply()
1562 Mul1.setIsKill(false); in combineFPFusedMultiply()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 3489 auto Mul1 = in emitReciprocalU64() local
3494 B.buildFMul(S32, Mul1, B.buildFConstant(S32, BitsToFloat(0x2f800000))); in emitReciprocalU64()
3499 B.buildFConstant(S32, BitsToFloat(0xcf800000)), Mul1); in emitReciprocalU64()
4055 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags); in legalizeFDIVFastIntrin() local
4057 B.buildFMul(Res, Sel, Mul1, Flags); in legalizeFDIVFastIntrin()
|
| D | AMDGPUISelLowering.cpp | 1856 SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp, in LowerUDIVREM64() local
1858 SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1, in LowerUDIVREM64()
1863 Mul1); in LowerUDIVREM64()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 29857 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, in LowerMULH() local
29871 SDValue Res = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, ShufMask); in LowerMULH()
47345 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
47347 DAG.getConstant(Mul1, DL, VT)); in combineMulSpecial()
|