| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 124 Register NewVR = MRI->createVirtualRegister(RC); in InsertNewDef() local
125 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR); in InsertNewDef()
236 Register NewVR; in RewriteUse() local
239 NewVR = GetValueAtEndOfBlockInternal(SourceBB); in RewriteUse()
241 NewVR = GetValueInMiddleOfBlock(UseMI->getParent()); in RewriteUse()
244 U.setReg(NewVR); in RewriteUse()
|
| D | TargetInstrInfo.cpp | 978 Register NewVR = MRI.createVirtualRegister(RC); in reassociateOps() local
979 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in reassociateOps()
996 BuildMI(*MF, MIMetadata(Prev), TII->get(NewPrevOpc), NewVR) in reassociateOps()
1002 std::swap(RegA, NewVR); in reassociateOps()
1009 .addReg(NewVR, getKillRegState(KillNewVR)) in reassociateOps()
|
| D | PeepholeOptimizer.cpp | 604 Register NewVR = MRI->createVirtualRegister(RC); in INITIALIZE_PASS_DEPENDENCY() local
606 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
611 UseMO->setReg(NewVR); in INITIALIZE_PASS_DEPENDENCY()
784 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI() local
787 TII.get(TargetOpcode::PHI), NewVR); in insertPHI()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 5709 Register NewVR = MRI.createVirtualRegister(RC); in genNeg() local
5711 BuildMI(MF, MIMetadata(Root), TII->get(MnegOpc), NewVR) in genNeg()
5716 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); in genNeg()
5718 return NewVR; in genNeg()
5730 Register NewVR = in genFusedMultiplyAccNeg() local
5733 FMAInstKind::Accumulator, &NewVR); in genFusedMultiplyAccNeg()
5757 Register NewVR = in genFusedMultiplyIdxNeg() local
5761 FMAInstKind::Indexed, &NewVR); in genFusedMultiplyIdxNeg()
5837 Register NewVR = MRI.createVirtualRegister(MRI.getRegClass(RegA)); in genSubAdd2SubSub() local
5849 BuildMI(MF, MIMetadata(Root), TII->get(Opcode), NewVR) in genSubAdd2SubSub()
[all …]
|
| D | AArch64ISelLowering.cpp | 22670 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
22680 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
22687 .addReg(NewVR); in insertCopiesSplitCSR()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 1385 Register NewVR = MRI->createVirtualRegister(RC); in generateInserts() local
1386 RegMap[VR] = NewVR; in generateInserts()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 8731 Register NewVR = in enforceOperandRCAlignment() local
8734 BuildMI(*BB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewVR) in enforceOperandRCAlignment()
8739 Op.setReg(NewVR); in enforceOperandRCAlignment()
8741 MI.addOperand(MachineOperand::CreateReg(NewVR, false, true)); in enforceOperandRCAlignment()
|
| D | SIISelLowering.cpp | 2366 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
2369 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
2376 .addReg(NewVR); in insertCopiesSplitCSR()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 21872 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
21882 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
21889 .addReg(NewVR); in insertCopiesSplitCSR()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 57770 Register NewVR = MRI->createVirtualRegister(RC); in insertCopiesSplitCSR() local
57780 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR) in insertCopiesSplitCSR()
57787 .addReg(NewVR); in insertCopiesSplitCSR()
|