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Searched refs:Order (Results 1 – 25 of 182) sorted by relevance

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/openbsd/src/gnu/llvm/libcxx/benchmarks/
Dmap.bench.cpp45 enum class Order { Sorted, Random }; enum
46 struct AllOrders : EnumValuesAsTuple<AllOrders, Order, 2> {
236 template <class Mode, class Order>
243 Order::value == ::Order::Random ? Shuffle::Keys : Shuffle::None, 1000); in run()
264 Order::value == ::Order::Random ? Shuffle::Keys in run()
272 return "BM_Insert" + baseName() + Mode::name() + Order::name(); in name()
355 template <class Mode, class Order>
362 Order::value == ::Order::Random ? Shuffle::Keys : Shuffle::None, 1000); in run()
383 Order::value == ::Order::Random ? Shuffle::Keys in run()
391 return "BM_InsertAssign" + baseName() + Mode::name() + Order::name(); in name()
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/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
59 return AO.Order[Pos];
67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos]))
90 AllocationOrder(SmallVector<MCPhysReg, 16> &&Hints, ArrayRef<MCPhysReg> Order, in AllocationOrder() argument
92 : Hints(std::move(Hints)), Order(Order), in AllocationOrder()
93 IterationLimit(HardHints ? 0 : static_cast<int>(Order.size())) {} in AllocationOrder()
102 assert(OrderLimit <= Order.size()); in getOrderLimitEnd()
111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create() local
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
49 assert(is_contained(Order, Hints[I]) && in create()
52 return AllocationOrder(std::move(Hints), Order, HardHints); in create()
DRegAllocGreedy.cpp395 AllocationOrder &Order, in tryAssign() argument
399 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign()
416 if (Order.isHint(Hint)) { in tryAssign()
439 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters); in tryAssign()
449 auto Order = in canReassign() local
452 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in canReassign()
528 const AllocationOrder &Order, in getOrderLimit() argument
530 unsigned OrderLimit = Order.getOrder().size(); in getOrderLimit()
544 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in getOrderLimit()
574 AllocationOrder &Order, in tryEvict() argument
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DRegisterClassInfo.cpp134 if (!RCI.Order) in compute()
135 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
160 RCI.Order[N++] = PhysReg; in compute()
173 RCI.Order[N++] = PhysReg; in compute()
193 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
DLocalStackSlotAllocation.cpp58 unsigned Order; member in __anonb9b65cd90111::FrameRef
62 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
65 return std::tie(LocalOffset, FrameIdx, Order) < in operator <()
66 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <()
304 unsigned Order = 0; in insertFrameReferenceRegisters() local
332 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
DMLRegallocEvictAdvisor.cpp295 const AllocationOrder &Order,
311 const LiveInterval &VirtReg, const AllocationOrder &Order,
422 const LiveInterval &VirtReg, const AllocationOrder &Order,
646 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
648 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
686 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
760 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidate()
1067 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidatePosition() argument
1073 VirtReg, Order, OrderLimit, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition()
1076 VirtReg, Order, CostPerUseLimit, FixedRegisters); in tryFindEvictionCandidatePosition()
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DRegAllocEvictionAdvisor.cpp276 const LiveInterval &VirtReg, const AllocationOrder &Order, in tryFindEvictionCandidate() argument
282 auto MaybeOrderLimit = getOrderLimit(VirtReg, Order, CostPerUseLimit); in tryFindEvictionCandidate()
294 for (auto I = Order.begin(), E = Order.getOrderLimitEnd(OrderLimit); I != E; in tryFindEvictionCandidate()
/openbsd/src/gnu/llvm/llvm/lib/Support/
DDynamicLibrary.cpp81 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
82 if (Order & SO_LoadOrder) { in LibLookup()
96 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
97 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
100 if (!Process || (Order & SO_LoadedFirst)) { in Lookup()
101 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
110 if (Order & SO_LoadedLast) { in Lookup()
111 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h734 void setIROrder(unsigned Order) { IROrder = Order; }
1084 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1086 IROrder(Order), debugLoc(std::move(dl)) {
1115 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1116 assert(Order >= 0 && "bad IROrder");
1263 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1285 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1446 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1448 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1504 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
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DScheduleDAG.h56 Order ///< Any other ordering dependency. enumerator
124 : Dep(S, Order), Contents(), Latency(0) { in SDep()
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
187 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
195 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak()
201 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
207 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster()
473 case Order: in overlaps()
DRegisterClassInfo.h36 std::unique_ptr<MCPhysReg[]> Order; member
41 return ArrayRef(Order.get(), NumRegs);
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DSDNodeDbgValue.h149 unsigned Order; variable
163 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect), in SDDbgValue()
219 unsigned getOrder() const { return Order; } in getOrder()
245 unsigned Order; variable
249 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
259 unsigned getOrder() const { return Order; } in getOrder()
DScheduleDAGSDNodes.cpp738 DenseMap<SDValue, Register> &VRBaseMap, unsigned Order) { in ProcessSDDbgValues() argument
761 if (Order != 0 && DVOrder != Order) in ProcessSDDbgValues()
786 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
787 if (!Order || Seen.count(Order)) { in ProcessSourceNode()
799 Seen.insert(Order); in ProcessSourceNode()
800 Orders.push_back({Order, NewInsn}); in ProcessSourceNode()
805 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
981 unsigned Order = Orders[i].first; in EmitSchedule() local
986 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1004 LastOrder = Order; in EmitSchedule()
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/openbsd/src/gnu/llvm/llvm/lib/Transforms/Scalar/
DStructurizeCFG.cpp250 SmallVector<RegionNode *, 8> Order; member in __anon311913f30111::StructurizeCFG
380 Order.resize(std::distance(GraphTraits<Region *>::nodes_begin(ParentRegion), in INITIALIZE_PASS_DEPENDENCY()
382 if (Order.empty()) in INITIALIZE_PASS_DEPENDENCY()
390 unsigned I = 0, E = Order.size(); in INITIALIZE_PASS_DEPENDENCY()
409 Order[I++] = N.first; in INITIALIZE_PASS_DEPENDENCY()
424 Nodes.insert(Order.begin() + I, Order.begin() + E - 1); in INITIALIZE_PASS_DEPENDENCY()
427 EntryNode.first = Order[E - 1]; in INITIALIZE_PASS_DEPENDENCY()
534 for (RegionNode *RN : reverse(Order)) { in collectInfos()
854 BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : in getNextFlow()
855 Order.back()->getEntry(); in getNextFlow()
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/openbsd/src/gnu/llvm/llvm/include/llvm/Frontend/OpenMP/
DOMPIRBuilder.h732 omp::OrderKind Order, ConstantInt *Simdlen,
1954 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo() argument
1956 : Flags(Flags), Order(Order), Kind(Kind) {} in OffloadEntryInfo()
1960 bool isValid() const { return Order != ~0u; } in isValid()
1961 unsigned getOrder() const { return Order; } in getOrder()
1980 unsigned Order = ~0u; variable
2014 explicit OffloadEntryInfoTargetRegion(unsigned Order, Constant *Addr, in OffloadEntryInfoTargetRegion() argument
2017 : OffloadEntryInfo(OffloadingEntryInfoTargetRegion, Order, Flags), in OffloadEntryInfoTargetRegion()
2035 unsigned Order);
2077 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar() argument
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/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64GenRegisterBankInfo.def147 ArrayRef<PartialMappingIdx> Order) {
148 if (Order.front() != FirstAlias)
150 if (Order.back() != LastAlias)
152 if (Order.front() > Order.back())
155 PartialMappingIdx Previous = Order.front();
157 for (const auto &Current : Order) {
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp57 static void addHints(ArrayRef<MCPhysReg> Order, in addHints() argument
64 for (MCPhysReg Reg : Order) in addHints()
68 for (MCPhysReg Reg : Order) in addHints()
75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
83 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
126 for (MCPhysReg OrderReg : Order) in getRegAllocationHints()
156 addHints(Order, Hints, RC, MRI); in getRegAllocationHints()
177 addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI); in getRegAllocationHints()
/openbsd/src/games/mille/
Dvarpush.c57 { (void *) &Order, sizeof Order }, in varpush()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUInsertDelayAlu.cpp241 SmallVector<const_iterator, 8> Order; in dump() local
242 Order.reserve(size()); in dump()
244 Order.push_back(I); in dump()
245 llvm::sort(Order, [](const const_iterator &A, const const_iterator &B) { in dump()
248 for (const_iterator I : Order) { in dump()
/openbsd/src/gnu/llvm/llvm/lib/Transforms/Utils/
DCodeLayout.cpp885 void concatChains(std::vector<uint64_t> &Order) { in concatChains() argument
920 Order.reserve(NumNodes); in concatChains()
923 Order.push_back(Block->Index); in concatChains()
978 const std::vector<uint64_t> &Order, const std::vector<uint64_t> &NodeSizes, in calcExtTspScore() argument
983 for (size_t Idx = 1; Idx < Order.size(); Idx++) { in calcExtTspScore()
984 Addr[Order[Idx]] = Addr[Order[Idx - 1]] + NodeSizes[Order[Idx - 1]]; in calcExtTspScore()
1009 std::vector<uint64_t> Order(NodeSizes.size()); in calcExtTspScore() local
1011 Order[Idx] = Idx; in calcExtTspScore()
1013 return calcExtTspScore(Order, NodeSizes, NodeCounts, EdgeCounts); in calcExtTspScore()
/openbsd/src/gnu/llvm/clang/lib/CodeGen/
DCGAtomic.cpp524 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp() argument
539 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
545 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
551 Val1, Val2, FailureOrder, Size, Order, Scope); in EmitAtomicOp()
565 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
570 FailureOrder, Size, Order, Scope); in EmitAtomicOp()
583 Load->setAtomic(Order, Scope); in EmitAtomicOp()
596 Store->setAtomic(Order, Scope); in EmitAtomicOp()
695 CGF.Builder.CreateAtomicRMW(Op, Ptr.getPointer(), LoadVal1, Order, Scope); in EmitAtomicOp()
726 uint64_t Size, llvm::AtomicOrdering Order, in EmitAtomicOp() argument
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/openbsd/src/gnu/llvm/llvm/tools/verify-uselistorder/
Dverify-uselistorder.cpp404 SmallDenseMap<const Use *, short, 16> Order; in shuffleValueUseLists() local
406 [&Order](const Use &L, const Use &R) { return Order[&L] < Order[&R]; }; in shuffleValueUseLists()
410 Order[&U] = I; in shuffleValueUseLists()
422 dbgs() << " - order: " << Order.lookup(&U) in shuffleValueUseLists()
/openbsd/src/gnu/llvm/llvm/lib/Bitcode/Writer/
DValueEnumerator.cpp796 SmallVector<MDIndex, 64> Order; in organizeMetadata() local
797 Order.reserve(MetadataMap.size()); in organizeMetadata()
799 Order.push_back(MetadataMap.lookup(MD)); in organizeMetadata()
807 llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) { in organizeMetadata()
817 for (unsigned I = 0, E = Order.size(); I != E && !Order[I].F; ++I) { in organizeMetadata()
818 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
826 if (MDs.size() == Order.size()) in organizeMetadata()
833 for (unsigned I = MDs.size(), E = Order.size(), ID = MDs.size(); I != E; in organizeMetadata()
835 unsigned F = Order[I].F; in organizeMetadata()
847 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenRegisters.h545 unsigned Order = 0; // Cache the sort key. member
787 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt() argument
788 return RegUnitSetOrder[Order]; in getRegSetIDAt()
791 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt() argument
792 return RegUnitSets[RegUnitSetOrder[Order]]; in getRegSetAt()

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