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Searched refs:PACKET3_SET_CONTEXT_REG_START (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dsi_enums.h263 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
Dsoc15d.h297 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
Dnvd.h322 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
Dvid.h344 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
Dcikd.h462 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
Dgfx_v7_0.c2490 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
2498 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
3900 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
3910 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
Dsid.h1849 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
Dgfx_v8_0.c1232 PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
1243 PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
4171 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
4179 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
Dgfx_v6_0.c2024 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_cp_gfx_start()
2869 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_get_csb_buffer()
Dgfx_v11_0.c830 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_get_csb_buffer()
840 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
3454 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_cp_gfx_start()
3462 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
Dgfx_v10_0.c4258 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_get_csb_buffer()
4268 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_get_csb_buffer()
6245 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_cp_gfx_start()
6253 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_cp_gfx_start()
Dgfx_v9_0.c1638 PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_get_csb_buffer()
3306 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_cp_gfx_start()
/openbsd/src/sys/dev/pci/drm/radeon/
Devergreen_cs.c2319 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
2321 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || in evergreen_packet3_check()
2630 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
3505 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_vm_packet3_check()
Dnid.h1273 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
Dsid.h1786 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
Dcikd.h1929 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
Devergreend.h1669 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
Dsi.c5728 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in si_get_csb_buffer()
Dcik.c6732 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in cik_get_csb_buffer()