| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 191 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
192 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
344 const TargetRegisterClass *getRegClass(unsigned RCID) const;
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| D | AMDGPUTargetTransformInfo.h | 118 unsigned getNumberOfRegisters(unsigned RCID) const;
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| D | SIInstrInfo.cpp | 4887 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass() argument
4893 switch (RCID) { in adjustAllocatableRegClass()
4895 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
4898 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
4901 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
4904 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
4907 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
4910 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
4917 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
4963 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local
[all …]
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| D | SIRegisterInfo.cpp | 3042 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
3043 switch ((int)RCID) { in getRegClass()
3052 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
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| D | AMDGPUTargetTransformInfo.cpp | 299 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
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| D | AMDGPUISelDAGToDAG.cpp | 378 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
380 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 913 unsigned RCID; in getRegClassConstraint() local
917 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
918 return TRI->getRegClass(RCID); in getRegClassConstraint()
1747 unsigned RCID = 0; in print() local
1749 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1751 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1753 OS << ":RC" << RCID; in print()
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| D | TargetInstrInfo.cpp | 1515 unsigned RCID = 0; in createMIROperandComment() local
1517 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in createMIROperandComment()
1519 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1521 OS << ":RC" << RCID; in createMIROperandComment()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 674 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
675 if (RCID != -1) { in printRegularOperand()
676 const MCRegisterClass RC = MRI.getRegClass(RCID); in printRegularOperand()
761 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
762 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 2208 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
2209 switch (RCID) { in getRegBitWidth()
2356 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
2357 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
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| D | AMDGPUBaseInfo.h | 1160 unsigned getRegBitWidth(unsigned RCID);
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 264 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline() argument
265 return isRegClass(RCID) || isInlinableImm(type); in isRegOrInline()
268 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
269 return isRegOrInline(RCID, type) || isLiteralImm(type); in isRegOrImmWithInputMods()
403 bool isRegClass(unsigned RCID) const;
407 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
408 return isRegOrInline(RCID, type) && !hasModifiers(); in isRegOrInlineNoMods()
2028 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
2029 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2648 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1596 unsigned RCID; in handleSpecialFP() local
1614 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 181 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local
183 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
1686 for (const unsigned RCID : in decomposeSubvectorInsertExtractToSubRegs()
1688 if (VecRegClassID > RCID && SubRegClassID <= RCID) { in decomposeSubvectorInsertExtractToSubRegs()
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