Searched refs:RSQ (Results 1 – 12 of 12) sorted by relevance
| /openbsd/src/gnu/usr.bin/binutils/opcodes/ |
| D | ChangeLog | 63 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
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| D | ppc-opc.c | 416 #define RSQ RS + 1 macro
421 #define RTQ RSQ + 1
4460 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
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| D | ChangeLog-0203 | 533 * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define.
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 421 RSQ, enumerator
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| D | AMDGPUInstrInfo.td | 115 def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
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| D | AMDGPUISelLowering.cpp | 4444 NODE_NAME_CASE(RSQ) in getTargetNodeName()
4561 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand); in getSqrtEstimate()
4865 case AMDGPUISD::RSQ: in isKnownNeverNaNForTargetNode()
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| D | SIISelLowering.cpp | 6890 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
6907 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
8907 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0)); in lowerFastUnsafeFDIV()
10075 return DCI.DAG.getNode(AMDGPUISD::RSQ, SDLoc(N), VT, in performRcpCombine()
10117 case AMDGPUISD::RSQ: in isCanonicalized()
11641 case AMDGPUISD::RSQ: in PerformDAGCombine()
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| D | R600ISelLowering.cpp | 566 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
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| D | AMDGPUISelDAGToDAG.cpp | 179 case AMDGPUISD::RSQ: in fp16SrcZerosHighBits()
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| /openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/ |
| D | ChangeLog-2004 | 540 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
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| D | ppc-opc.c | 425 #define RSQ RS + 1 macro
430 #define RTQ RSQ + 1
4561 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
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| D | ChangeLog-0203 | 533 * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define.
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