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Searched refs:Rm (Results 1 – 25 of 41) sorted by relevance

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/openbsd/src/gnu/usr.bin/binutils/gas/doc/
Dc-sh.texi245 Rm @r{another numbered register}
252 add Rm,Rn mac.w @@Rm+,@@Rn+
253 addc Rm,Rn mov #imm,Rn
254 addv Rm,Rn mov Rm,Rn
255 and #imm,R0 mov.b Rm,@@(R0,Rn)
256 and Rm,Rn mov.b Rm,@@-Rn
257 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
258 bf disp8 mov.b @@(disp,Rm),R0
260 bsr disp12 mov.b @@(R0,Rm),Rn
261 bt disp8 mov.b @@Rm+,Rn
[all …]
/openbsd/src/gnu/usr.bin/binutils-2.17/gas/doc/
Dc-sh.texi249 Rm @r{another numbered register}
256 add Rm,Rn mac.w @@Rm+,@@Rn+
257 addc Rm,Rn mov #imm,Rn
258 addv Rm,Rn mov Rm,Rn
259 and #imm,R0 mov.b Rm,@@(R0,Rn)
260 and Rm,Rn mov.b Rm,@@-Rn
261 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
262 bf disp8 mov.b @@(disp,Rm),R0
264 bsr disp12 mov.b @@(R0,Rm),Rn
265 bt disp8 mov.b @@Rm+,Rn
[all …]
/openbsd/src/sys/arch/arm64/arm64/
Ddisasm.c745 uint64_t sf, uint64_t Rm, uint64_t option, uint64_t imm3, in extendreg_common() argument
757 PRINTF("%s, %s", SREGNAME(sf, Rn), ZREGNAME(r, Rm)); in extendreg_common()
788 uint64_t sf, uint64_t shift, uint64_t Rm, uint64_t imm6, in shiftreg_common() argument
801 ZREGNAME(sf, Rm)); in shiftreg_common()
806 ZREGNAME(sf, Rm)); in shiftreg_common()
812 ZREGNAME(sf, Rm)); in shiftreg_common()
836 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_b_common() argument
851 ZREGNAME(r, Rm), in regoffset_b_common()
859 ZREGNAME(r, Rm), in regoffset_b_common()
868 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_h_common() argument
[all …]
/openbsd/src/sys/arch/sh/include/
Dlocore.h160 #define __EXCEPTION_BLOCK(Rn, Rm) ;\ argument
164 stc sr, Rm ;\
165 or Rn, Rm ;\
166 ldc Rm, sr /* block exceptions */
168 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\ argument
173 stc sr, Rm ;\
174 and Rn, Rm ;\
175 ldc Rm, sr /* unblock exceptions */
181 #define __INTR_MASK(Rn, Rm) ;\ argument
184 stc sr, Rm ;\
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMInstrThumb.td395 let Inst{6-3} = 0b1111; // Rm = pc
454 // ADD <Rm>, sp
466 // ADD sp, <Rm>
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
468 "add", "\t$Rdn, $Rm", []>,
471 bits<4> Rm;
473 let Inst{6-3} = Rm;
484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
487 bits<4> Rm;
488 let Inst{6-3} = Rm;
[all …]
DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
524 bits<4> Rm;
527 let Inst{3-0} = Rm;
534 bits<4> Rm;
537 let Inst{3-0} = Rm;
544 bits<4> Rm;
547 let Inst{3-0} = Rm;
583 bits<4> Rm;
587 let Inst{3-0} = Rm;
[all …]
DARMInstrInfo.td1548 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1549 iir, opc, "\t$Rd, $Rn, $Rm",
1550 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1554 bits<4> Rm;
1560 let Inst{3-0} = Rm;
1621 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1622 iir, opc, "\t$Rd, $Rn, $Rm",
1627 bits<4> Rm;
1630 let Inst{3-0} = Rm;
1683 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
632 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
637 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
638 "vld1", Dt, "$Vd, $Rn, $Rm",
649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
654 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
655 "vld1", Dt, "$Vd, $Rn, $Rm",
676 let Rm = 0b1111;
685 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
[all …]
DARMInstrCDE.td85 dag Rm;
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
155 bits<4> Rm;
160 let Inst{15-12} = Rm{3-0};
171 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
179 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
476 let Rm = (ins regclass:$Vm);
484 let Rm = (ins regclass:$Qm);
498 let Iops2 = !con(IOpsPrefix, ops.Rm);
[all …]
DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
22 // Rd after a minimum of three cycles after the result in Rm and Rs is available
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrFormats.td803 // {11-0} imm12/Rm
821 // {11-0} imm12/Rm
840 // {13} 1 == Rm, 0 == imm12
842 // {11-0} imm12/Rm
860 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
867 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
892 // {13} 1 == imm8, 0 == Rm
896 // {3-0} imm3_0/Rm
918 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
925 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td66 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
68 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
69 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
71 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
82 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
84 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
85 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
87 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
98 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
100 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]
DAArch64InstrFormats.td1921 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
1923 bits<5> Rm;
1927 let Inst{4-0} = Rm;
2236 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
2237 asm, "\t$Rd, $Rn, $Rm", "",
2238 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2242 bits<5> Rm;
2244 let Inst{20-16} = Rm;
2290 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2291 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
[all …]
DAArch64InstrInfo.td760 def AArch64addp : PatFrags<(ops node:$Rn, node:$Rm),
761 [(AArch64addp_n node:$Rn, node:$Rm),
762 (int_aarch64_neon_addp node:$Rn, node:$Rm)]>;
769 def AArch64faddp : PatFrags<(ops node:$Rn, node:$Rm),
770 [(AArch64addp_n node:$Rn, node:$Rm),
771 (int_aarch64_neon_faddp node:$Rn, node:$Rm)]>;
1089 (v4bf16 V64:$Rm),
1093 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
1121 (AArch64duplane32 (v4i32 V128:$Rm),
1271 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
[all …]
DSVEInstrFormats.td1509 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
1510 asm, "\t$Zdn, $Rm",
1513 bits<5> Rm;
1518 let Inst{9-5} = Rm;
5010 : I<(outs), (ins rt:$Rn, rt:$Rm),
5011 asm, "\t$Rn, $Rm",
5014 bits<5> Rm;
5019 let Inst{20-16} = Rm;
5030 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
5031 asm, "\t$Pd, $Rn, $Rm",
[all …]
DSMEInstrFormats.td379 bits<5> Rm;
387 let Inst{20-16} = Rm;
403 gpr_ty:$Rm),
404 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
410 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
411 …tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
556 bits<5> Rm;
564 let Inst{20-16} = Rm;
581 GPR64sp:$Rn, gpr_ty:$Rm),
582 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1664 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1669 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1702 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1707 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
2046 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
2108 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2151 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
2177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
2209 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
2242 if (type && Rm == 15) in DecodeAddrMode3Instruction()
[all …]
/openbsd/src/gnu/llvm/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp1288 uint32_t Rm; // the source register in EmulateMOVRdRm() local
1294 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
1301 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
1308 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1311 if (setflags && (BadReg(Rd) || BadReg(Rm))) in EmulateMOVRdRm()
1315 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13))) in EmulateMOVRdRm()
1320 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1331 uint32_t result = ReadCoreReg(Rm, &success); in EmulateMOVRdRm()
1339 else if (Rd == GetFramePointerRegisterNumber() && Rm == 13) in EmulateMOVRdRm()
1344 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm); in EmulateMOVRdRm()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1012 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
1040 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1061 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1614 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1628 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1634 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1640 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1646 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1652 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1658 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
[all …]
/openbsd/src/regress/lib/libcrypto/x509/bettertls/certificates/
D1720.crt21 40mm4qIzAEM9EGyg6djCOb2YHg2PZm2K1cEwt5v1QHQY1gwBhUtCwFA+579Rm/am
D2090.key21 B4fMexmWXhnYqvUfPtCNSQKBgEwIReU/0Rm/b6cuAhh9B5uLc5NiztkqMaGB7SQy
D2525.key23 o45Wd9byZ1LyWEC0gpI5R98n717UGLAXfGJq8kkyQCE2s4zsrD+Rm+bFawgp0Hrc
D1378.chain18 Rm/81hpKkp5pHTr4QODEQAAqG7e8ef9/DRI2hpSuVGfIrS5MIzrr4e0tgNmz4usr
D1173.chain19 i1r1uYKZk/XcWA+1TY+bwcW9hxvwrQS8af+D0CoSPWTf5OQ2nW5fA7R7h+0Hb/Rm
/openbsd/src/gnu/llvm/llvm/docs/TableGen/
Dindex.rst240 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
243 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
247 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
251 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,

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