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Searched refs:Rs (Results 1 – 25 of 94) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
120 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_lo)>;
121 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG $Rs, isub_hi)>;
246 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
247 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
248 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
249 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
250 def ToAext64: OutPatFrag<(ops node:$Rs),
251 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
253 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
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DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
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DHexagonRegisterInfo.td90 // Rs - system registers
91 class Rs<bits<7> num, string n,
289 def SGP0 : Rs<0, "sgp0", ["s0"]>, DwarfRegNum<[144]>;
290 def SGP1 : Rs<1, "sgp1", ["s1"]>, DwarfRegNum<[145]>;
291 def STID : Rs<2, "stid", ["s2"]>, DwarfRegNum<[146]>;
292 def ELR : Rs<3, "elr", ["s3"]>, DwarfRegNum<[147]>;
293 def BADVA0 : Rs<4, "badva0", ["s4"]>, DwarfRegNum<[148]>;
294 def BADVA1 : Rs<5, "badva1", ["s5"]>, DwarfRegNum<[149]>;
295 def SSR : Rs<6, "ssr", ["s6"]>, DwarfRegNum<[150]>;
296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>;
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DHexagonConstExtenders.cpp293 Register Rs; member
298 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {} in ExtExpr()
301 return Rs.Reg == 0; in trivial()
304 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg; in operator ==()
310 if (Rs != Ex.Rs) in operator <()
311 return Rs < Ex.Rs; in operator <()
446 : Rs(R), HRI(I) {} in PrintRegister()
447 HCE::Register Rs; member
453 if (P.Rs.Reg != 0) in operator <<()
454 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
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DHexagonPatternsHVX.td300 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
301 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
302 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
303 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
304 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
305 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
348 def: Pat<(VecI8 (splat_vector I32:$Rs)), (PS_vsplatrb $Rs)>;
349 def: Pat<(VecI16 (splat_vector I32:$Rs)), (PS_vsplatrh $Rs)>;
350 def: Pat<(VecI32 (splat_vector I32:$Rs)), (PS_vsplatrw $Rs)>;
351 def: Pat<(VecPI8 (splat_vector I32:$Rs)), (Rep (PS_vsplatrb $Rs))>;
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DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
302 // Rd=[cround|round](Rs,Rt)[:sat]
303 // Rd=[cround|round](Rs,#u5)[:sat]
328 // Rdd=vmpyb[s]u(Rs,Rt)
332 // Rxx+=vmpyb[s]u(Rs,Rt)
DHexagonSplitDouble.cpp103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second; in isInduction() local
148 if (Rs.find(Reg) != Rs.end()) in isInduction()
374 Register Rs = MI->getOperand(1).getReg(); in profit() local
376 return profit(Rs) + profit(Rt); in profit()
476 USet &Rs) { in collectIndRegsForLoop() argument
560 Rs.insert(DP.begin(), End); in collectIndRegsForLoop()
561 Rs.insert(CmpR1); in collectIndRegsForLoop()
562 Rs.insert(CmpR2); in collectIndRegsForLoop()
566 dump_partition(dbgs(), Rs, *TRI); in collectIndRegsForLoop()
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DHexagonPseudo.td42 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
51 let Inst{27} = Rs;
209 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
210 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
211 bits<5> Rs;
217 let Inst{20-16} = Rs;
286 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
336 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
355 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
432 class Vsplatr_template : InstHexagon<(outs HvxVR:$Vd), (ins IntRegs:$Rs),
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DHexagonGenInsert.cpp128 RegisterSet &insert(const RegisterSet &Rs) { in insert()
129 return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); in insert()
131 RegisterSet &remove(const RegisterSet &Rs) { in remove()
132 return static_cast<RegisterSet&>(BitVector::reset(Rs)); in remove()
155 bool includes(const RegisterSet &Rs) const { in includes()
157 return !Rs.BitVector::test(*this); in includes()
159 bool intersects(const RegisterSet &Rs) const { in intersects()
160 return BitVector::anyCommon(Rs); in intersects()
1211 void stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero,
1248 void IFOrdering::stats(const RegisterSet &Rs, unsigned &Size, unsigned &Zero, in stats() argument
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/openbsd/src/gnu/usr.bin/binutils-2.17/cpu/
Dcris.cpu253 ((Rs INT -1))
261 ((Rs INT -1) (Rd INT -1))
264 ((Rs INT -1) (Rd INT -1))
267 ((Rs INT -1) (Rd INT -1))
273 ((Rs INT -1))
291 ((Rd INT -1) (Rs INT -1))
298 ((Rs INT -1))
305 ((Rs INT -1))
1536 ; Rs := source operand, register addressing mode
1537 (dnop Rs "Source general register" () h-gr f-source)
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/openbsd/src/regress/usr.bin/mandoc/mdoc/Rs/
Dallch.out_lint1 mandoc: allch.in:15:1: WARNING: invalid content in Rs block: text
2 mandoc: allch.in:20:2: WARNING: invalid content in Rs block: Em
3 mandoc: allch.in:21:1: WARNING: invalid content in Rs block: text
4 mandoc: allch.in:36:1: WARNING: invalid content in Rs block: text
5 mandoc: allch.in:37:2: WARNING: invalid content in Rs block: Em
6 mandoc: allch.in:42:1: WARNING: invalid content in Rs block: text
Dparagraph.out_html2 initial reference: <span class="Rs"><span class="RsA">author name</span>,
4 <p class="Pp">in a paragraph: <span class="Rs"><span class="RsA">another
11 <p class="Pp"><span class="Rs"><span class="RsA">author name</span>,
14 <p class="Pp"><span class="Rs"><span class="RsA">another author</span>,
Dempty.out_lint1 mandoc: empty.in:10:2: WARNING: empty reference block: Rs
2 mandoc: empty.in:15:2: WARNING: empty reference block: Rs
Dargs.out_lint1 mandoc: args.in:10:5: ERROR: skipping all arguments: Rs bogus
2 mandoc: args.in:15:5: ERROR: skipping all arguments: Rs Sy
Dempty.out_markdown5 **Rs-empty** - empty reference blocks
Dthree_authors.out_markdown5 **Rs-three\_authors** - listing three authors in a reference block
Dargs.out_markdown5 **Rs-args** - arguments on a reference block header line
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
223 Rs = L.getOperand(1); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
268 CompoundInsn->addOperand(Rs); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
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/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp578 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
581 Rs))); in DecodeDAHIDATIMMR6()
583 Rs))); in DecodeDAHIDATIMMR6()
592 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
595 Rs))); in DecodeDAHIDATI()
597 Rs))); in DecodeDAHIDATI()
617 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
622 if (Rs >= Rt) { in DecodeAddiGroupBranch()
625 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
633 Rs))); in DecodeAddiGroupBranch()
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/openbsd/src/gnu/llvm/compiler-rt/lib/xray/
Dxray_mips.cpp40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
43 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() argument
155 switch (Rs) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
184 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeI()
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
190 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeII()
/openbsd/src/gnu/llvm/llvm/lib/Analysis/
DScalarEvolutionDivision.cpp147 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
159 Rs.push_back(R); in visitAddExpr()
164 Remainder = Rs[0]; in visitAddExpr()
169 Remainder = SE.getAddExpr(Rs); in visitAddExpr()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1629 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1639 TmpInst.addOperand(Rs); in processInstruction()
1649 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1659 TmpInst.addOperand(Rs); in processInstruction()
1669 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1679 TmpInst.addOperand(Rs); in processInstruction()
1692 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1709 TmpInst.addOperand(Rs); in processInstruction()
1725 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1727 TmpInst.addOperand(Rs); in processInstruction()
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/openbsd/src/usr.bin/mandoc/
Dmandoc.css166 .Rs { font-style: normal;
277 .Ic, code.In, .Lb, .Lk, .Ms, .Mt, .Nd, code.Nm, .Pa, .Rs,
304 .Rs::before { content: "Rs"; }
319 .Pa::before, .Rs::before,
341 .Rs:hover::before, h2.Sh:hover::before, h3.Ss:hover::before, .St:hover::before,

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