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Searched refs:Rt (Results 1 – 25 of 47) sorted by relevance

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/openbsd/src/gnu/llvm/clang/lib/Headers/
Dhvx_hexagon_protos.h63 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) argument
129 …fine Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(_… argument
151 …m_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRA… argument
162 …RIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_W… argument
173 …RIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WR… argument
184 …mem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRA… argument
536 #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) argument
569 … Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__b… argument
580 …or_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(… argument
591 …ne Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(… argument
[all …]
/openbsd/src/sys/arch/arm64/arm64/
Ddisasm.c836 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_b_common() argument
849 ZREGNAME(0, Rt), in regoffset_b_common()
857 ZREGNAME(0, Rt), in regoffset_b_common()
868 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_h_common() argument
881 ZREGNAME(0, Rt), in regoffset_h_common()
887 ZREGNAME(0, Rt), in regoffset_h_common()
895 ZREGNAME(0, Rt), in regoffset_h_common()
906 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_w_common() argument
919 ZREGNAME(1, Rt), in regoffset_w_common()
925 ZREGNAME(1, Rt), in regoffset_w_common()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
28 (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
253 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
254 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
333 (MI RsPred:$Rs, RtPred:$Rt)>;
342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
739 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
740 (Output RsPred:$Rs, RtPred:$Rt)>;
743 : OutPatFrag<(ops node:$Rs, node:$Rt),
[all …]
DHexagonPatternsHVX.td135 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$Off))),
136 (MI I32:$Rt, imm:$Off)>;
137 def: Pat<(ResType (Load I32:$Rt)),
138 (MI I32:$Rt, 0)>;
162 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
163 (MI I32:$Rt, 0)>;
164 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
165 (MI I32:$Rt, imm:$Off)>;
207 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$Off)),
208 (MI I32:$Rt, imm:$Off, Value:$Vs)>;
[all …]
DHexagonPatternsV65.td14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
48 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
59 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
70 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
61 //Rxx^=asr(Rss,Rt)
63 //Rxx^=asl(Rss,Rt)
65 //Rxx^=lsr(Rss,Rt)
67 //Rxx^=lsl(Rss,Rt)
[all …]
DHexagonAsmPrinter.cpp376 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
377 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
378 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
383 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
387 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
388 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
389 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
394 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
399 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
400 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMInstrThumb2.td1177 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
1178 opc, ".w\t$Rt, $addr",
1179 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
1181 bits<4> Rt;
1189 let Inst{15-12} = Rt;
1194 def i8 : T2Ii8n <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1195 opc, "\t$Rt, $addr",
1196 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1198 bits<4> Rt;
1207 let Inst{15-12} = Rt;
[all …]
DARMInstrInfo.td2007 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2008 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
2009 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
2010 bits<4> Rt;
2014 let Inst{15-12} = Rt;
2017 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
2018 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
2019 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
2020 bits<4> Rt;
2025 let Inst{15-12} = Rt;
[all …]
DARMInstrVFP.td1158 (outs GPR:$Rt), (ins SPR:$Sn),
1159 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
1160 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1164 bits<4> Rt;
1170 let Inst{15-12} = Rt;
1182 (outs SPR:$Sn), (ins GPR:$Rt),
1183 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
1184 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1189 bits<4> Rt;
1194 let Inst{15-12} = Rt;
[all …]
DARMInstrThumb.td692 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
693 "ldr", "\t$Rt, $addr",
694 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
697 bits<3> Rt;
699 let Inst{10-8} = Rt;
706 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
707 "ldr", "\t$Rt, $addr",
708 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
710 bits<3> Rt;
712 let Inst{10-8} = Rt;
[all …]
DARMInstrFormats.td662 bits<4> Rt;
668 let Inst{15-12} = Rt;
677 bits<4> Rt;
686 let Inst{3-0} = Rt;
716 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
717 bits<4> Rt;
724 let Inst{15-12} = Rt;
788 bits<4> Rt;
794 let Inst{15-12} = Rt;
856 bits<4> Rt;
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp618 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
622 if (Rs >= Rt) { in DecodeAddiGroupBranch()
625 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
636 Rt))); in DecodeAddiGroupBranch()
646 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
650 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
653 Rt))); in DecodePOP35GroupBranchMMR6()
657 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
662 Rt))); in DecodePOP35GroupBranchMMR6()
667 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
211 Rt = L.getOperand(0); in getCompoundInsn()
216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
222 Rt = L.getOperand(0); in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
237 Rt = L.getOperand(2); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
250 Rt = L.getOperand(2); in getCompoundInsn()
256 CompoundInsn->addOperand(Rt); in getCompoundInsn()
263 Rt = L.getOperand(2); in getCompoundInsn()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1105 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
1114 Inst.addOperand(MCOperand::createImm(Rt)); in DecodeUnsignedLdStInstruction()
1124 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1131 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1135 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1139 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1143 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1147 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1151 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
1164 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1574 [(set GPR64:$Rt, (int_aarch64_tstart))]>;
1581 def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
2081 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
2113 def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
2117 def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$offset)),
2118 (LDG GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
2120 def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
2122 def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
2123 (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
2124 def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
[all …]
DAArch64InstrFormats.td1544 // System instructions which do not have an Rt register.
1551 // System instructions which have an Rt register.
1556 bits<5> Rt;
1557 let Inst{4-0} = Rt;
1577 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1578 bits<5> Rt;
1579 let Inst{4-0} = Rt;
1586 : RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
1717 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
1718 "mrs", "\t$Rt, $systemreg"> {
[all …]
/openbsd/src/gnu/llvm/compiler-rt/lib/xray/
Dxray_mips.cpp41 uint32_t Rt, in encodeInstruction() argument
43 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
Dxray_mips64.cpp42 uint32_t Rt, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp2045 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
2070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2104 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2207 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
2216 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
2228 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
2240 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2252 if (Rt == 15) in DecodeAddrMode3Instruction()
2254 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2269 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1390 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local
1393 TmpInst.addOperand(Rt); in processInstruction()
1394 TmpInst.addOperand(Rt); in processInstruction()
1811 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
1812 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1817 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1822 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1831 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local
1832 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1837 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/openbsd/src/regress/lib/libcrypto/x509/bettertls/certificates/
D1304.key25 Rt+Y0Pa7+FvECMA5T+FznIR5d4rG4xZLRDZWv5pe95ENMgVjOW1bw94NO4CxpueY
D328.key11 v3FYLwor+dbqKUdQpFx7J5GYAIDHqDm89bSdWQzTxge+pBYRT+wNwXFY0Xtwt+Rt
D1584.key17 Rt+mp0L+xhWFJCQc7viPT03x0ZUfkyc1nmcRHk1UoGEFPCrad3K+5TTmgdYmzVqo

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