| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIPeepholeSDWA.cpp | 113 using namespace AMDGPU::SDWA;
368 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
375 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 && in convertToSDWA()
376 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) { in convertToSDWA()
440 getDstSel() != AMDGPU::SDWA::DWORD) { in convertToSDWA()
1067 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1077 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); in convertToSDWA()
1087 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1097 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1104 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
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| D | VOPInstructions.td | 459 def SDWA {
497 // GFX9 adds two features to SDWA:
498 // 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.
502 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
508 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
510 // gfx9 SDWA basic encoding
530 // gfx9 SDWA-A
543 // gfx9 SDWA-B
570 let SDWA = 1;
579 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
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| D | SIDefines.h | 49 SDWA = 1 << 14, enumerator
274 SDWA = 2, enumerator
763 namespace SDWA {
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| D | AMDGPU.td | 415 "Support SDWA (Sub-DWORD Addressing) extension"
421 "Support OMod with SDWA (Sub-DWORD Addressing) extension"
427 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
433 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
439 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
445 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
1373 string SDWA = "SDWA";
1397 let Name = AMDGPUAsmVariants.SDWA;
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| D | SIInstrFormats.td | 34 field bit SDWA = 0;
173 let TSFlags{14} = SDWA;
242 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| D | SIInstrInfo.td | 26 int SDWA = 2;
1639 // instructions with SDWA extension
1835 // Return type of input modifiers operand specified input operand for SDWA
2059 // Ins for SDWA
2107 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
2112 // Outs for SDWA
2342 0, // NumSrcArgs == 3 - No SDWA for VOP3
2344 0, // 64-bit dst - No SDWA for 64-bit operands
2374 // Function that checks if instruction supports DPP and SDWA
2828 // Maps ordinary instructions to their SDWA counterparts
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| D | SIInstrInfo.h | 451 return MI.getDesc().TSFlags & SIInstrFlags::SDWA; in isSDWA()
455 return get(Opcode).TSFlags & SIInstrFlags::SDWA; in isSDWA()
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| D | SIInstrInfo.cpp | 918 .addImm(DstLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()
919 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()
920 .addImm(AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) in copyPhysReg()
921 .addImm(SrcLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()
922 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()
4319 DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) { in verifyInstruction()
7995 SDWA = 2, enumerator
8057 if (get(Opcode).TSFlags & SIInstrFlags::SDWA) { in pseudoToMCOpcode()
8060 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
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| D | VOP1Instructions.td | 114 // We only want to set this on the basic, non-SDWA or DPP forms.
608 (inst_sdwa 0, $src, 0, 0, SDWA.WORD_1),
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| D | AMDGPUInstructionSelector.cpp | 2200 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel in selectG_TRUNC()
2201 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_TRUNC()
2202 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel in selectG_TRUNC()
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| D | GCNHazardRecognizer.cpp | 919 if (DstSel->getImm() == AMDGPU::SDWA::DWORD) in checkVALUHazards()
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| D | VOP3Instructions.td | 1052 // (they do not support SDWA or DPP).
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | AMDGPUInstructionSyntax.rst | 169 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
182 *SDWA* encoding _sdwa
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| D | AMDGPUModifierSyntax.rst | 1435 SDWA Modifiers
1524 SDWA Operand Modifiers
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 442 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
473 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
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| D | AMDGPUInstPrinter.cpp | 377 else if (Flags & SIInstrFlags::SDWA) in printVOPDst()
1050 using namespace llvm::AMDGPU::SDWA; in printSDWASel()
1089 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3252 (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) ) in checkTargetMatchPredicate()
3266 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
3277 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, in getAllVariants()
3301 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA, in getMatchedVariants()
3475 SIInstrFlags::VOP3 | SIInstrFlags::VOP3P | SIInstrFlags::SDWA)) && in validateConstantBusLimitations()
3781 if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc)) in validateMovrels()
4068 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
4082 if (IsRevOpcode(Opcode) || (Desc.TSFlags & SIInstrFlags::SDWA)) in validateLdsDirect()
8867 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
8901 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 1768 using namespace AMDGPU::SDWA; in decodeSDWASrc()
1816 using namespace AMDGPU::SDWA; in decodeSDWAVopcDst()
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| /openbsd/src/gnu/llvm/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX1030.rst | 758 SDWA section in Instructions
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| D | AMDGPUAsmGFX10.rst | 778 SDWA section in Instructions
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