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Searched refs:SETEQ (Results 1 – 25 of 61) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td73 defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DISDOpcodes.h1448 SETEQ, // 1 X 0 0 1 True if equal enumerator
1474 return Code == SETEQ || Code == SETNE; in isIntEqualitySetCC()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp317 case ISD::SETEQ: in softenSetCCOperands()
3731 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithAnd()
3761 Cond == ISD::SETEQ ? ISD::SETGE : ISD::SETLT); in foldSetCCWithAnd()
3848 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
3850 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
3917 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in optimizeSetCCByHoistingAndByConstFromLogicalShift()
3990 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"); in foldSetCCWithBinOp()
4063 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4070 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) { in simplifySetCCWithCTPOP()
4083 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in simplifySetCCWithCTPOP()
[all …]
DLegalizeIntegerTypes.cpp2489 N->getOperand(2), ISD::SETEQ); in ExpandIntegerResult()
2803 ISD::SETEQ); in ExpandShiftWithUnknownAmountBit()
2910 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ); in ExpandIntRes_MINMAX()
3981 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ); in ExpandIntRes_MULFIX()
3987 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ); in ExpandIntRes_MULFIX()
3994 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ); in ExpandIntRes_MULFIX()
4000 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ); in ExpandIntRes_MULFIX()
4772 Opc == ISD::FSHL ? ISD::SETNE : ISD::SETEQ); in ExpandIntRes_FunnelShift()
4887 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { in IntegerExpandSetCCOperands()
5018 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ, in IntegerExpandSetCCOperands()
[all …]
DSelectionDAGDumper.cpp467 case ISD::SETEQ: return "seteq"; in getOperationName()
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVE.h212 case ISD::SETEQ: in intCondCode2Icc()
242 case ISD::SETEQ: in fpCondCode2Fcc()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DAnalysis.cpp211 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
223 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
240 case ISD::SETEQ: in getICmpCondCode()
DTargetLoweringBase.cpp670 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
671 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
672 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
673 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td310 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
314 def : PatSetCC<FPR64, any_fsetcc, SETEQ, FEQ_D>;
322 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ),
329 def : Pat<(strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ),
DRISCVInstrInfoZfh.td310 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
314 def : PatSetCC<FPR16, any_fsetcc, SETEQ, FEQ_H>;
322 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ),
329 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ),
DRISCVISelDAGToDAG.h118 case ISD::SETEQ: in getRISCVCCForIntCC()
DRISCVInstrInfoF.td559 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
563 def : PatSetCC<FPR32, any_fsetcc, SETEQ, FEQ_S>;
571 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ),
578 def : Pat<(strict_fsetccs FPR32:$rs1, FPR32:$rs1, SETEQ),
DRISCVInstrInfoVSDPatterns.td680 defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
688 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
698 defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSEQ", SETEQ>;
953 defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
DRISCVInstrInfoVVLPatterns.td1442 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>;
1450 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>;
1460 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>;
1645 defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp3175 case ISD::SETEQ: { in get32BitZExtCompare()
3349 case ISD::SETEQ: { in get32BitSExtCompare()
3520 case ISD::SETEQ: { in get64BitZExtCompare()
3677 case ISD::SETEQ: { in get64BitSExtCompare()
3976 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4020 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
4068 case ISD::SETEQ: in SelectCC()
4095 case ISD::SETEQ: in SelectCC()
4144 case ISD::SETEQ: in getPredicateForSetCC()
4181 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
[all …]
DPPCInstrInfo.td3403 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3501 defm : ExtSetCCPat<SETEQ,
3611 defm : ExtSetCCShiftPat<SETEQ,
3630 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3632 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3646 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3658 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3670 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3672 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3686 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp811 case ISD::SETEQ: in IntCondCCodeToICC()
1259 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS()
1316 SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSRL_PARTS()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td1412 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1418 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1425 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1431 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h1248 X86_INTRINSIC_DATA(sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ),
1265 X86_INTRINSIC_DATA(sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ),
1273 X86_INTRINSIC_DATA(sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ),
1320 X86_INTRINSIC_DATA(sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ),
/openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp199 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ }, in MSP430TargetLowering()
205 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ }, in MSP430TargetLowering()
1050 case ISD::SETEQ: in EmitCMP()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUInstructions.td325 def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;
362 def COND_EQ : PatFrags<(ops), [(OtherVT SETEQ), (OtherVT SETUEQ)]>;
DAMDGPUISelLowering.cpp1426 case ISD::SETEQ: in combineFMinMaxLegacy()
1922 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ); in LowerUDIVREM64()
1944 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ); in LowerUDIVREM64()
1978 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
1982 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ); in LowerUDIVREM64()
2756 SDValue Lo40Set = DAG.getSelectCC(DL, MaskedSig, Zero, Zero, One, ISD::SETEQ); in LowerFP_TO_FP16()
2790 One, Zero, ISD::SETEQ); in LowerFP_TO_FP16()
2799 I, V, ISD::SETEQ); in LowerFP_TO_FP16()
3632 if (CCOpcode == ISD::SETEQ && in performCtlz_CttzCombine()
DR600ISelLowering.cpp751 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
761 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
1871 case ISD::SETEQ: { in PerformDAGCombine()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td537 …i8 (zext (nxv16i1 (AArch64setcc_z (nxv16i1 (SVEAllActive):$Pg), nxv16i8:$Op2, (SVEDup0), SETEQ)))),
539 …8i16 (zext (nxv8i1 (AArch64setcc_z (nxv8i1 (SVEAllActive):$Pg), nxv8i16:$Op2, (SVEDup0), SETEQ)))),
541 …4i32 (zext (nxv4i1 (AArch64setcc_z (nxv4i1 (SVEAllActive):$Pg), nxv4i32:$Op2, (SVEDup0), SETEQ)))),
543 …2i64 (zext (nxv2i1 (AArch64setcc_z (nxv2i1 (SVEAllActive):$Pg), nxv2i64:$Op2, (SVEDup0), SETEQ)))),
1883 defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq", SETEQ, SETEQ>;
1901 defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq", SETEQ, SETEQ>;
1902 defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne", SETNE, SETEQ>;
1910 defm FCMEQ_PPzZZ : sve_fp_3op_p_pd_cc<0b010, "fcmeq", SETOEQ, SETEQ, SETOEQ, SETEQ>;
1920 defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq", SETOEQ, SETEQ, SETOEQ, SETEQ>;
/openbsd/src/gnu/llvm/llvm/lib/Target/BPF/
DBPFInstrInfo.td85 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
105 [{return (N->getZExtValue() == ISD::SETEQ);}]>;

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