| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVBaseInfo.h | 419 inline static bool isValidSEW(unsigned SEW) { in isValidSEW() argument
420 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024; in isValidSEW()
428 unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
450 inline static unsigned encodeSEW(unsigned SEW) { in encodeSEW() argument
451 assert(isValidSEW(SEW) && "Unexpected SEW value"); in encodeSEW()
452 return Log2_32(SEW) - 3; in encodeSEW()
466 unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
|
| D | RISCVBaseInfo.cpp | 135 unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, in encodeVTYPE() argument
137 assert(isValidSEW(SEW) && "Invalid SEW"); in encodeVTYPE()
139 unsigned VSEWBits = encodeSEW(SEW); in encodeVTYPE()
190 unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { in getSEWLMULRatio() argument
198 assert(SEW >= 8 && "Unexpected SEW value"); in getSEWLMULRatio()
199 return (SEW * 8) / LMul; in getSEWLMULRatio()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVInsertVSETVLI.cpp | 134 bool SEW = false; member
142 return SEW || LMUL || SEWLMULRatio || TailPolicy || MaskPolicy; in usedVTYPE()
152 SEW = true; in demandVTYPE()
177 OS << "SEW=" << SEW << ", "; in print()
202 if (Used.SEW && in areCompatibleVTYPEs()
261 Res.SEW = false; in getDemanded()
276 Res.SEW = false; in getDemanded()
307 uint8_t SEW = 0; member in __anon4c2f49c10111::VSETVLIInfo
348 unsigned getSEW() const { return SEW; } in getSEW()
379 SEW = RISCVVType::getSEW(VType); in setVTYPE()
[all …]
|
| D | RISCVISelDAGToDAG.cpp | 557 unsigned SEW = in selectVSETVLI() local
562 unsigned VTypeI = RISCVVType::encodeVTYPE(VLMul, SEW, /*TailAgnostic*/ true, in selectVSETVLI()
1153 SDValue SEW = CurDAG->getTargetConstant( in Select() local
1160 ReplaceNode(Node, CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW)); in Select()
1167 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1170 {Cmp, Cmp, VL, SEW})); in Select()
1232 SDValue SEW = CurDAG->getTargetConstant( in Select() local
1259 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}), in Select()
1279 {MaskedOff, Src1, Src2, V0, VL, SEW, Glue}), in Select()
1826 SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT); in Select() local
[all …]
|
| D | RISCVInstrInfo.cpp | 1721 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in verifyInstruction() local
1722 if (!RISCVVType::isValidSEW(SEW)) { in verifyInstruction()
2038 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in createMIROperandComment() local
2039 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW"); in createMIROperandComment()
2040 OS << "e" << SEW; in createMIROperandComment()
|
| D | RISCVInstrInfoVPseudos.td | 188 int SEW = Sew;
284 // This functor is used to obtain the int vector type that has the same SEW and
296 // {SEW, VLMul} values set a valid VType to deal with this mask type.
297 // we assume SEW=1 and set corresponding LMUL. vsetvli insertion will
298 // look for SEW=1 to optimize based on surrounding instructions.
299 int SEW = 1;
310 // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
4907 defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");
4927 defvar wtiSEW = !mul(vti.SEW, 2);
|
| D | RISCVInstrInfoVVLPatterns.td | 939 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1");
1005 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
1025 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
1582 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
|
| D | RISCVISelLowering.cpp | 5524 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT); in lowerVectorIntrinsicScalars() local
5527 I32VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVLMAX, SEW, in lowerVectorIntrinsicScalars()
5539 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT); in lowerVectorIntrinsicScalars() local
5545 SEW, LMUL); in lowerVectorIntrinsicScalars()
|
| /openbsd/src/gnu/llvm/clang/include/clang/Basic/ |
| D | riscv_vector.td | 89 // vector type (SEW and LMUL) and EEW (8/16/32/64), computes its
92 // (SEW=16, LMUL=4) and Log2EEW is 3 (EEW=8), and then equivalent vector
95 // (FixedSEW:Value): Given a vector type (SEW and LMUL), and computes another
96 // vector type which only changed SEW as given value. Ignore to define a new
97 // builtin if its equivalent type has illegal lmul or the SEW does not changed.
98 // (SFixedLog2LMUL:Value): Smaller Fixed Log2LMUL. Given a vector type (SEW
102 // (LFixedLog2LMUL:Value): Larger Fixed Log2LMUL. Given a vector type (SEW
1610 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
1752 // Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW
1756 // Widening signed integer add/subtract, 2*SEW = SEW +/- SEW
[all …]
|
| D | RISCVVTypes.def | 31 // - ElBits is the size of one element in bits (SEW).
|
| /openbsd/src/gnu/llvm/clang/lib/CodeGen/ |
| D | CGDebugInfo.cpp | 772 unsigned SEW = CGM.getContext().getTypeSize(Info.ElementType); in CreateType() local
776 unsigned FixedSize = ElementCount * SEW; in CreateType()
797 SEW / 8, // SEW is in bits. in CreateType()
|