Searched refs:SMULL (Results 1 – 9 of 9) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 307 SMULL, enumerator
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| D | AArch64ISelLowering.cpp | 2495 MAKE_CASE(AArch64ISD::SMULL) in getTargetNodeName()
4531 return AArch64ISD::SMULL; in selectUmullSmull()
4555 return AArch64ISD::SMULL; in selectUmullSmull()
4598 return AArch64ISD::SMULL; in selectUmullSmull()
6192 N1.getOpcode() == AArch64ISD::SMULL) in isReassocProfitable()
18078 return DAG.getNode(AArch64ISD::SMULL, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
21526 case AArch64ISD::SMULL: in PerformDAGCombine()
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| D | AArch64InstrInfo.td | 730 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull,
5415 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", AArch64smull>;
6698 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull", AArch64smull>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 278 "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
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| D | ARMScheduleSwift.td | 281 (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>;
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| D | ARMScheduleA57.td | 290 // Multiply long: SMULL, UMULL
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| D | ARMInstrInfo.td | 4368 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4390 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
6411 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6428 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
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| D | ARMScheduleA9.td | 2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 8334 case ARM::SMULL: in validateInstruction()
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