Searched refs:SiFive7 (Results 1 – 3 of 3) sorted by relevance
1 //==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=//11 // SiFive7 machine model for scheduling and other instruction cost heuristics.13 let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.24 // The SiFive7 microarchitecture has two pipelines: A and B.
39 SiFive7, enumerator
530 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",