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Searched refs:SlotIdx (Results 1 – 5 of 5) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DRegisterPressure.cpp582 SlotIndex SlotIdx = LIS.getInstructionIndex(MI); in detectDeadDefs() local
587 LiveQueryResult LRQ = LR->Query(SlotIdx); in detectDeadDefs()
798 SlotIndex SlotIdx; in recede() local
800 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot(); in recede()
834 LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx); in recede()
864 SlotIndex SlotIdx; in recedeSkipDebugValues() local
866 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot(); in recedeSkipDebugValues()
870 static_cast<IntervalPressure&>(P).openTop(SlotIdx); in recedeSkipDebugValues()
886 SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot(); in recede() local
887 RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx); in recede()
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DScheduleDAGInstrs.cpp821 SlotIndex SlotIdx = LIS->getInstructionIndex(MI); in buildSchedGraph() local
822 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx); in buildSchedGraph()
DMachineScheduler.cpp1430 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); in scheduleMI() local
1431 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI); in scheduleMI()
1464 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); in scheduleMI() local
1465 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI); in scheduleMI()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DGCNIterativeScheduler.cpp378 auto SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); in scheduleRegion() local
379 RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI); in scheduleRegion()
DGCNSchedStrategy.cpp1199 SlotIndex SlotIdx = DAG.LIS->getInstructionIndex(*MI).getRegSlot(); in revertScheduling() local
1200 RegOpers.adjustLaneLiveness(*DAG.LIS, DAG.MRI, SlotIdx, MI); in revertScheduling()