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Searched refs:TRC (Results 1 – 25 of 32) sorted by relevance

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/openbsd/src/usr.bin/banner/
Dbanner.c83 #define TRC(q) (((q)-' ')&0177) macro
91 case TRC('_'): in dropit()
92 case TRC(';'): in dropit()
93 case TRC(','): in dropit()
94 case TRC('g'): in dropit()
95 case TRC('j'): in dropit()
96 case TRC('p'): in dropit()
97 case TRC('q'): in dropit()
98 case TRC('y'): in dropit()
124 c = TRC(cc); in scan_out()
/openbsd/src/usr.sbin/lpd/
Dlp_banner.c1098 #define TRC(q) (((q)-' ')&0177) macro
1105 case TRC('_'): in dropit()
1106 case TRC(';'): in dropit()
1107 case TRC(','): in dropit()
1108 case TRC('g'): in dropit()
1109 case TRC('j'): in dropit()
1110 case TRC('p'): in dropit()
1111 case TRC('q'): in dropit()
1112 case TRC('y'): in dropit()
1132 d = dropit(c = TRC(cc = *sp++)); in lp_banner()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) { in usesRegClass() argument
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
141 return TRC->contains(Reg); in usesRegClass()
269 const TargetRegisterClass *TRC = in optimizeSDPattern() local
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
432 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
DARMLoadStoreOptimizer.cpp2434 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2435 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2436 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2736 const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); in AdjustBaseAndOffset() local
2737 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
2793 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
2794 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
2796 TRC = TII->getRegClass(MCID, 2, TRI, *MF); in createPostIncLoadStore()
2797 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
DARMISelLowering.cpp10659 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass in SetupEntryBlockForSjLj() local
10678 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10684 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10690 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10708 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10713 Register NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10718 Register NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10723 Register NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10729 Register NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
10744 Register NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
[all …]
/openbsd/src/usr.sbin/lpr/lpd/
Dprintjob.c1051 #define TRC(q) (((q)-' ')&0177) macro
1066 d = dropit(c = TRC(cc = *sp++)); in scan_out()
1092 case TRC('_'): in dropit()
1093 case TRC(';'): in dropit()
1094 case TRC(','): in dropit()
1095 case TRC('g'): in dropit()
1096 case TRC('j'): in dropit()
1097 case TRC('p'): in dropit()
1098 case TRC('q'): in dropit()
1099 case TRC('y'): in dropit()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp499 const TargetRegisterClass *TRC = in EmitSubregNode() local
518 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
524 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
538 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
655 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
657 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp500 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
501 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
DLiveDebugVariables.cpp1541 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
1542 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
1853 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in emitDebugValues() local
1856 unsigned regSizeInBits = TRI->getRegSizeInBits(*TRC); in emitDebugValues()
1864 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
DRegAllocPBQP.cpp617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
625 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp61 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
64 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
DWebAssemblyISelLowering.cpp545 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in LowerCallResults() local
546 IsFuncrefCall = (TRC == &WebAssembly::FUNCREFRegClass); in LowerCallResults()
/openbsd/src/gnu/llvm/clang/include/clang/AST/
DASTNodeTraverser.h429 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
430 Visit(TRC); in VisitFunctionDecl()
DDecl.h2570 if (auto *TRC = getTrailingRequiresClause()) in getAssociatedConstraints() local
2571 AC.push_back(TRC); in getAssociatedConstraints()
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86AvoidStoreForwardingBlocks.cpp557 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
559 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h1198 const TargetRegisterClass &TRC, in isOfRegClass() argument
1202 return RC == &TRC; in isOfRegClass()
1204 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
/openbsd/src/gnu/llvm/clang/lib/Sema/
DSemaTemplateVariadic.cpp969 if (Expr *TRC = D.getTrailingRequiresClause()) in containsUnexpandedParameterPacks() local
970 if (TRC->containsUnexpandedParameterPack()) in containsUnexpandedParameterPacks()
DSemaLookup.cpp5477 TypoDiagnosticGenerator TDG, TypoRecoveryCallback TRC, CorrectTypoKind Mode, in CorrectTypoDelayed() argument
5504 return createDelayedTypo(std::move(Consumer), std::move(TDG), std::move(TRC), in CorrectTypoDelayed()
5814 TypoRecoveryCallback TRC, in createDelayedTypo() argument
5821 State.RecoveryHandler = std::move(TRC); in createDelayedTypo()
/openbsd/src/gnu/llvm/clang/include/clang/Sema/
DDeclSpec.h2531 void setTrailingRequiresClause(Expr *TRC) { in setTrailingRequiresClause() argument
2532 TrailingRequiresClause = TRC; in setTrailingRequiresClause()
2534 SetRangeEnd(TRC->getEndLoc()); in setTrailingRequiresClause()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() argument
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp3246 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isQForm() local
3247 return TRC == &AArch64::FPR128RegClass || in isQForm()
3248 TRC == &AArch64::FPR128_loRegClass; in isQForm()
3265 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isFpOrNEON() local
3266 return TRC == &AArch64::FPR128RegClass || in isFpOrNEON()
3267 TRC == &AArch64::FPR128_loRegClass || in isFpOrNEON()
3268 TRC == &AArch64::FPR64RegClass || in isFpOrNEON()
3269 TRC == &AArch64::FPR64_loRegClass || in isFpOrNEON()
3270 TRC == &AArch64::FPR32RegClass || TRC == &AArch64::FPR16RegClass || in isFpOrNEON()
3271 TRC == &AArch64::FPR8RegClass; in isFpOrNEON()
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp994 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
997 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
/openbsd/src/gnu/llvm/clang/lib/AST/
DDeclTemplate.cpp241 if (const Expr *TRC = FD->getTrailingRequiresClause()) in getAssociatedConstraints() local
242 AC.push_back(TRC); in getAssociatedConstraints()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp2101 const TargetRegisterClass *TRC; in createVR() local
2103 TRC = &Hexagon::PredRegsRegClass; in createVR()
2105 TRC = &Hexagon::IntRegsRegClass; in createVR()
2107 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
2112 Register NewReg = MRI.createVirtualRegister(TRC); in createVR()
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp1725 const TargetRegisterClass *TRC = in SelectInlineAsmMemoryOperand() local
1728 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); in SelectInlineAsmMemoryOperand()

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