| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 93 const TargetRegisterClass *
94 getLargestLegalSuperClass(const TargetRegisterClass *RC,
126 const TargetRegisterClass *getPointerRegClass(
133 const TargetRegisterClass *
134 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
173 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
176 const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) const;
179 const TargetRegisterClass *
183 static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
186 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass()
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| D | SIRegisterInfo.cpp | 125 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); in SGPRSpillBuilder()
199 const TargetRegisterClass &RC = in prepare()
435 const TargetRegisterClass *
436 SIRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
922 const TargetRegisterClass *SIRegisterInfo::getPointerRegClass( in getPointerRegClass()
930 const TargetRegisterClass *
931 SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
1326 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
2271 const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass in eliminateFrameIndex()
2364 const TargetRegisterClass *RC = IsSALU && !LiveSCC in eliminateFrameIndex()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 45 class TargetRegisterClass {
49 using sc_iterator = const TargetRegisterClass* const *;
124 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
136 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
238 using regclass_iterator = const TargetRegisterClass * const *;
279 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
285 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
291 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
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| D | RegisterClassInfo.h | 75 void compute(const TargetRegisterClass *RC) const;
78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
127 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
135 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
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| D | RegisterScavenging.h | 31 class TargetRegisterClass; variable
136 BitVector getRegsAvailable(const TargetRegisterClass *RC);
140 Register FindUnusedReg(const TargetRegisterClass *RC) const;
172 Register scavengeRegister(const TargetRegisterClass *RC,
175 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
189 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
234 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
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| D | LiveStacks.h | 32 class TargetRegisterClass; variable
47 std::map<int, const TargetRegisterClass *> S2RCMap;
66 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
84 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
86 std::map<int, const TargetRegisterClass *>::const_iterator I = in getIntervalRegClass()
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| D | RegAllocCommon.h | 16 class TargetRegisterClass; variable
20 const TargetRegisterClass &RC)> RegClassFilterFunc;
25 const TargetRegisterClass &) { in allocateAllRegClasses() argument
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| D | FastISel.h | 57 class TargetRegisterClass; variable
385 const TargetRegisterClass *RC);
390 const TargetRegisterClass *RC, unsigned Op0);
395 const TargetRegisterClass *RC, unsigned Op0,
401 const TargetRegisterClass *RC, unsigned Op0,
407 const TargetRegisterClass *RC, unsigned Op0,
413 const TargetRegisterClass *RC, unsigned Op0,
419 const TargetRegisterClass *RC,
425 const TargetRegisterClass *RC, unsigned Op0,
431 const TargetRegisterClass *RC, uint64_t Imm);
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| D | MachineSSAUpdater.h | 26 class TargetRegisterClass; variable
44 const TargetRegisterClass *VRC;
65 void Initialize(const TargetRegisterClass *RC);
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 60 const TargetRegisterClass *
61 getMatchingSuperRegClass(const TargetRegisterClass *A,
62 const TargetRegisterClass *B,
65 const TargetRegisterClass *
66 getSubClassWithSubReg(const TargetRegisterClass *RC,
69 const TargetRegisterClass *
70 getLargestLegalSuperClass(const TargetRegisterClass *RC,
73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
75 const TargetRegisterClass *SrcRC,
80 const TargetRegisterClass *
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| D | X86RegisterInfo.cpp | 84 const TargetRegisterClass *
85 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg()
96 const TargetRegisterClass *
97 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, in getMatchingSuperRegClass()
98 const TargetRegisterClass *B, in getMatchingSuperRegClass()
109 const TargetRegisterClass *
110 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
125 const TargetRegisterClass *Super = RC; in getLargestLegalSuperClass()
126 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); in getLargestLegalSuperClass()
176 const TargetRegisterClass *
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 194 const TargetRegisterClass *
195 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { in getAllocatableClass()
201 const TargetRegisterClass *SubRC = getRegClass(It.getID()); in getAllocatableClass()
211 const TargetRegisterClass *
218 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
219 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
229 const TargetRegisterClass *
236 const TargetRegisterClass *BestRC = nullptr; in getMinimalPhysRegClassLLT()
237 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT()
249 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
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| D | CriticalAntiDepBreaker.cpp | 71 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
89 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
119 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
126 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
196 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
205 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
206 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
211 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) in PrescanInstruction()
240 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) { in PrescanInstruction()
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| D | MachineRegisterInfo.cpp | 57 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass()
67 static const TargetRegisterClass *
69 const TargetRegisterClass *OldRC, in constrainRegClass()
70 const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
73 const TargetRegisterClass *NewRC = in constrainRegClass()
83 const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( in constrainRegClass()
84 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass()
104 else if (RegCB.is<const TargetRegisterClass *>() != in constrainRegAttrs()
105 ConstrainingRegCB.is<const TargetRegisterClass *>()) in constrainRegAttrs()
107 else if (RegCB.is<const TargetRegisterClass *>()) { in constrainRegAttrs()
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| D | RegisterBank.cpp | 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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| D | RegisterCoalescer.h | 22 class TargetRegisterClass; variable
57 const TargetRegisterClass *NewRC = nullptr;
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.h | 23 class TargetRegisterClass; variable
63 const TargetRegisterClass *
64 getSubClassWithSubReg(const TargetRegisterClass *RC,
102 const TargetRegisterClass *
105 const TargetRegisterClass *
106 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
134 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
141 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
142 unsigned SubReg, const TargetRegisterClass *DstRC,
143 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 171 const TargetRegisterClass *
174 const TargetRegisterClass *
175 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
177 const TargetRegisterClass *
178 getLargestLegalSuperClass(const TargetRegisterClass *RC,
181 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
233 const TargetRegisterClass *SrcRC,
235 const TargetRegisterClass *DstRC,
237 const TargetRegisterClass *NewRC,
240 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| D | ThumbRegisterInfo.h | 29 const TargetRegisterClass *
30 getLargestLegalSuperClass(const TargetRegisterClass *RC,
33 const TargetRegisterClass *
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.h | 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
54 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
55 unsigned SubReg, const TargetRegisterClass *DstRC,
56 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
68 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
72 const TargetRegisterClass *RC) const;
76 const TargetRegisterClass *
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| D | HexagonVLIWPacketizer.h | 25 class TargetRegisterClass; variable
123 const TargetRegisterClass *RC);
126 const TargetRegisterClass *RC);
131 const TargetRegisterClass *RC);
134 const TargetRegisterClass *RC);
146 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.h | 135 const TargetRegisterClass *
144 const TargetRegisterClass *
145 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
169 const TargetRegisterClass *SrcRC,
171 const TargetRegisterClass *DstRC,
173 const TargetRegisterClass *NewRC,
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.h | 25 class TargetRegisterClass; variable
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
73 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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| D | MipsInstrInfo.h | 38 class TargetRegisterClass; variable
139 const TargetRegisterClass *RC, in storeRegToStackSlot()
147 int FrameIndex, const TargetRegisterClass *RC, in loadRegFromStackSlot()
156 const TargetRegisterClass *RC,
163 const TargetRegisterClass *RC,
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