| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 350 USUBSAT, enumerator
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| D | TargetLowering.h | 2720 case ISD::USUBSAT: in isBinOp()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 3446 { ISD::USUBSAT, MVT::v32i16, { 1 } }, in getIntrinsicInstrCost()
3447 { ISD::USUBSAT, MVT::v64i8, { 1 } }, in getIntrinsicInstrCost()
3514 { ISD::USUBSAT, MVT::v16i32, { 2 } }, // pmaxud + psubd in getIntrinsicInstrCost()
3515 { ISD::USUBSAT, MVT::v2i64, { 2 } }, // pmaxuq + psubq in getIntrinsicInstrCost()
3516 { ISD::USUBSAT, MVT::v4i64, { 2 } }, // pmaxuq + psubq in getIntrinsicInstrCost()
3517 { ISD::USUBSAT, MVT::v8i64, { 2 } }, // pmaxuq + psubq in getIntrinsicInstrCost()
3528 { ISD::USUBSAT, MVT::v32i16, { 2 } }, in getIntrinsicInstrCost()
3529 { ISD::USUBSAT, MVT::v64i8, { 2 } }, in getIntrinsicInstrCost()
3649 { ISD::USUBSAT, MVT::v16i16, { 1 } }, in getIntrinsicInstrCost()
3650 { ISD::USUBSAT, MVT::v32i8, { 1 } }, in getIntrinsicInstrCost()
[all …]
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| D | X86ISelLowering.cpp | 1062 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal); in X86TargetLowering()
1066 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal); in X86TargetLowering()
1068 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom); in X86TargetLowering()
1069 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom); in X86TargetLowering()
1477 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1481 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1484 setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom); in X86TargetLowering()
1486 setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom); in X86TargetLowering()
1832 setOperationAction(ISD::USUBSAT, VT, HasBWI ? Legal : Custom); in X86TargetLowering()
24719 SDValue Result = DAG.getNode(ISD::USUBSAT, dl, VT, Op0, Op1); in LowerVSETCCWithSUBUS()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 408 case ISD::USUBSAT: in LegalizeOp()
881 case ISD::USUBSAT: in Expand()
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| D | SelectionDAGDumper.cpp | 329 case ISD::USUBSAT: return "usubsat"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 203 case ISD::USUBSAT: in PromoteIntegerResult()
876 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSHLSAT()
895 if (Opcode == ISD::USUBSAT) in PromoteIntRes_ADDSUBSHLSAT()
896 return DAG.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted, in PromoteIntRes_ADDSUBSHLSAT()
2535 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | TargetLowering.cpp | 9370 unsigned SubOpcode = NumSubElts <= NElts ? ISD::SUB : ISD::USUBSAT; in clampDynamicVectorIndex()
9499 isOperationLegal(ISD::USUBSAT, VT)) { in expandIntMINMAX()
9501 DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); in expandIntMINMAX()
9506 isOperationLegal(ISD::USUBSAT, VT)) { in expandIntMINMAX()
9508 DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); in expandIntMINMAX()
9542 if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { in expandAddSubSat()
9565 case ISD::USUBSAT: in expandAddSubSat()
9596 if (Opcode == ISD::USUBSAT) { in expandAddSubSat()
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| D | SelectionDAG.cpp | 3761 case ISD::USUBSAT: { in computeKnownBits()
5658 case ISD::USUBSAT: return C1.usub_sat(C2); in FoldValue()
6206 case ISD::USUBSAT: in getNode()
6215 if (Opcode == ISD::SSUBSAT || Opcode == ISD::USUBSAT) in getNode()
6545 case ISD::USUBSAT: in getNode()
6570 case ISD::USUBSAT: in getNode()
11657 SDValue Hi = getNode(ISD::USUBSAT, DL, VT, N, HalfNumElts); in SplitEVL()
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| D | DAGCombiner.cpp | 1695 case ISD::USUBSAT: return visitSUBSAT(N); in visit()
2588 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2595 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), in visitADDLike()
3366 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3382 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3389 !(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT))) in foldSubToUSubSat()
6174 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), SignMask); in foldAndToUsubsat()
6644 if (hasOperation(ISD::USUBSAT, VT)) in visitAND()
11443 if (hasOperation(ISD::USUBSAT, VT)) { in visitVSELECT()
11480 return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); in visitVSELECT()
[all …]
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| D | LegalizeVectorTypes.cpp | 137 case ISD::USUBSAT: in ScalarizeVectorResult()
1113 case ISD::USUBSAT: in SplitVectorResult()
3959 case ISD::USUBSAT: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 1146 case ISD::USUBSAT: in LegalizeOp()
3447 case ISD::USUBSAT: in ExpandNode()
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| D | SelectionDAGBuilder.cpp | 6622 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 809 ISD::SSUBSAT, ISD::USUBSAT, in initActions()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 213 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
274 setOperationAction(ISD::USUBSAT, VT, Legal); in addMVEVectorTypes()
1135 setOperationAction(ISD::USUBSAT, MVT::i8, Custom); in ARMTargetLowering()
1137 setOperationAction(ISD::USUBSAT, MVT::i16, Custom); in ARMTargetLowering()
5069 case ISD::USUBSAT: in LowerADDSUBSAT()
5085 case ISD::USUBSAT: in LowerADDSUBSAT()
7808 case ISD::USUBSAT: in IsQRMVEInstruction()
10491 case ISD::USUBSAT: in LowerOperation()
10595 case ISD::USUBSAT: in ReplaceNodeResults()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 451 setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Legal); in SITargetLowering()
482 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering()
662 ISD::UADDSAT, ISD::USUBSAT, ISD::SADDSAT, ISD::SSUBSAT}, in SITargetLowering()
681 ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
4780 case ISD::USUBSAT: in LowerOperation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 241 setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT}, in RISCVTargetLowering()
636 {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal); in RISCVTargetLowering()
894 {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, in RISCVTargetLowering()
4200 case ISD::USUBSAT: in LowerOperation()
7917 case ISD::USUBSAT: { in ReplaceNodeResults()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 431 def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1109 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
1266 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
18243 return convertMergedOpToPredOp(N, ISD::USUBSAT, DAG, true); in performIntrinsicCombine()
18254 return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 764 setOperationAction(ISD::USUBSAT, VT, Legal); in PPCTargetLowering()
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