Searched refs:VECREDUCE_FMIN (Results 1 – 13 of 13) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1280 VECREDUCE_FMIN, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 443 case ISD::VECREDUCE_FMIN: in LegalizeOp()
945 case ISD::VECREDUCE_FMIN: in Expand()
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| D | SelectionDAGDumper.cpp | 493 case ISD::VECREDUCE_FMIN: return "vecreduce_fmin"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 143 case ISD::VECREDUCE_FMIN: in SoftenFloatResult()
2305 case ISD::VECREDUCE_FMIN: in PromoteFloatResult()
2669 case ISD::VECREDUCE_FMIN: in SoftPromoteHalfResult()
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| D | LegalizeVectorTypes.cpp | 697 case ISD::VECREDUCE_FMIN: in ScalarizeVectorOperand()
2884 case ISD::VECREDUCE_FMIN: in SplitVectorOperand()
5845 case ISD::VECREDUCE_FMIN: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1201 case ISD::VECREDUCE_FMIN: in LegalizeOp()
3866 case ISD::VECREDUCE_FMIN: in ExpandNode()
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| D | SelectionDAGBuilder.cpp | 9848 Res = DAG.getNode(ISD::VECREDUCE_FMIN, dl, VT, Op1, SDFlags); in visitVectorReduce()
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| D | SelectionDAG.cpp | 454 case ISD::VECREDUCE_FMIN: in getVecReduceBaseOpcode()
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| D | DAGCombiner.cpp | 1827 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N); in visit()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 872 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL}, in initActions()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1127 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in AArch64TargetLowering()
1394 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in AArch64TargetLowering()
1794 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in addTypeForStreamingSVE()
1920 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in addTypeForFixedLengthSVE()
6003 case ISD::VECREDUCE_FMIN: in LowerOperation()
13247 case ISD::VECREDUCE_FMIN: in LowerVECREDUCE()
13273 case ISD::VECREDUCE_FMIN: { in LowerVECREDUCE()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 359 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); in addMVEVectorTypes()
382 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom); in addMVEVectorTypes()
386 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom); in addMVEVectorTypes()
10221 case ISD::VECREDUCE_FMIN: BaseOpcode = ISD::FMINNUM; break; in LowerVecReduce()
10506 case ISD::VECREDUCE_FMIN: in LowerOperation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 518 ISD::VECREDUCE_FADD, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_FMIN, in RISCVTargetLowering()
4026 case ISD::VECREDUCE_FMIN: in LowerOperation()
6073 case ISD::VECREDUCE_FMIN: in getRVVFPReductionOpAndOperands()
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