Searched refs:VECREDUCE_OR (Results 1 – 14 of 14) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1287 VECREDUCE_OR, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 434 case ISD::VECREDUCE_OR: in LegalizeOp()
936 case ISD::VECREDUCE_OR: in Expand()
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| D | SelectionDAGDumper.cpp | 486 case ISD::VECREDUCE_OR: return "vecreduce_or"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 244 case ISD::VECREDUCE_OR: in PromoteIntegerResult()
1716 case ISD::VECREDUCE_OR: in PromoteIntegerOperand()
2239 case ISD::VECREDUCE_OR: in getExtendForIntVecReduction()
2292 else if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 && in PromoteIntOp_VECREDUCE()
2293 !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_OR, InVT) && in PromoteIntOp_VECREDUCE()
2553 case ISD::VECREDUCE_OR: in ExpandIntegerResult()
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| D | LegalizeVectorTypes.cpp | 690 case ISD::VECREDUCE_OR: in ScalarizeVectorOperand()
2877 case ISD::VECREDUCE_OR: in SplitVectorOperand()
5838 case ISD::VECREDUCE_OR: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1194 case ISD::VECREDUCE_OR: in LegalizeOp()
3859 case ISD::VECREDUCE_OR: in ExpandNode()
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| D | SelectionDAG.cpp | 433 case ISD::VECREDUCE_OR: in getVecReduceBaseOpcode()
5601 return getNode(ISD::VECREDUCE_OR, DL, VT, Operand); in getNode()
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| D | DAGCombiner.cpp | 1820 case ISD::VECREDUCE_OR: in visit()
24750 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
24765 if ((Opcode == ISD::VECREDUCE_OR && in visitVECREDUCE()
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| D | SelectionDAGBuilder.cpp | 9827 Res = DAG.getNode(ISD::VECREDUCE_OR, dl, VT, Op1); in visitVectorReduce()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 513 ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in RISCVTargetLowering()
558 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
835 {ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT, in RISCVTargetLowering()
4019 case ISD::VECREDUCE_OR: in LowerOperation()
5884 case ISD::VECREDUCE_OR: in getRVVReductionOp()
5898 Op.getOpcode() == ISD::VECREDUCE_OR || in lowerVectorMaskVecReduction()
5941 case ISD::VECREDUCE_OR: in lowerVectorMaskVecReduction()
8130 case ISD::VECREDUCE_OR: in ReplaceNodeResults()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 869 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, in initActions()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1250 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1303 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1519 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in AArch64TargetLowering()
1921 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addTypeForFixedLengthSVE()
5995 case ISD::VECREDUCE_OR: in LowerOperation()
13214 Op.getOpcode() == ISD::VECREDUCE_OR || in LowerVECREDUCE()
13231 case ISD::VECREDUCE_OR: in LowerVECREDUCE()
20291 LHS = DAG.getNode(ISD::VECREDUCE_OR, DL, MVT::i1, LHS->getOperand(0)); in performSETCCCombine()
23393 case ISD::VECREDUCE_OR: in LowerPredReductionToSVE()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 301 setOperationAction(ISD::VECREDUCE_OR, VT, Custom); in addMVEVectorTypes()
10218 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break; in LowerVecReduce()
10501 case ISD::VECREDUCE_OR: in LowerOperation()
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