Searched refs:VECREDUCE_SMIN (Results 1 – 15 of 15) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1290 VECREDUCE_SMIN, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 437 case ISD::VECREDUCE_SMIN: in LegalizeOp()
939 case ISD::VECREDUCE_SMIN: in Expand()
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| D | SelectionDAGDumper.cpp | 489 case ISD::VECREDUCE_SMIN: return "vecreduce_smin"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 247 case ISD::VECREDUCE_SMIN: in PromoteIntegerResult()
1719 case ISD::VECREDUCE_SMIN: in PromoteIntegerOperand()
2248 case ISD::VECREDUCE_SMIN: in getExtendForIntVecReduction()
2556 case ISD::VECREDUCE_SMIN: in ExpandIntegerResult()
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| D | LegalizeVectorTypes.cpp | 693 case ISD::VECREDUCE_SMIN: in ScalarizeVectorOperand()
2880 case ISD::VECREDUCE_SMIN: in SplitVectorOperand()
5841 case ISD::VECREDUCE_SMIN: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1197 case ISD::VECREDUCE_SMIN: in LegalizeOp()
3862 case ISD::VECREDUCE_SMIN: in ExpandNode()
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| D | SelectionDAG.cpp | 442 case ISD::VECREDUCE_SMIN: in getVecReduceBaseOpcode()
5598 case ISD::VECREDUCE_SMIN: in getNode()
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| D | SelectionDAGBuilder.cpp | 9836 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); in visitVectorReduce()
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| D | DAGCombiner.cpp | 1823 case ISD::VECREDUCE_SMIN: in visit()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 870 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in initActions()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1136 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
1254 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
1509 setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
1797 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in addTypeForStreamingSVE()
1924 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in addTypeForFixedLengthSVE()
5998 case ISD::VECREDUCE_SMIN: in LowerOperation()
13235 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
13261 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
22095 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 514 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, in RISCVTargetLowering()
906 ISD::VECREDUCE_SMIN, ISD::VECREDUCE_UMAX, in RISCVTargetLowering()
4016 case ISD::VECREDUCE_SMIN: in LowerOperation()
5880 case ISD::VECREDUCE_SMIN: in getRVVReductionOp()
8134 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VEISelLowering.cpp | 351 ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMIN, in initVPUActions()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 469 def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 297 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal); in addMVEVectorTypes()
13081 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMIN || in PerformSELECTCombine()
13082 FalseVal->getOpcode() == ISD::VECREDUCE_SMIN) && in PerformSELECTCombine()
13105 case ISD::VECREDUCE_SMIN: in PerformSELECTCombine()
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