| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | AMDGPUInstructionSyntax.rst | 168 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
179 *VOP1*, *VOP2* and *VOPC* (32-bit) encoding _e32
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| D | AMDGPUOperandSyntax.rst | 124 VOP1, VOP2 and VOPC instructions may currently access only 128 low 16-bit registers using the synta…
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| D | AMDGPUUsage.rst | 14539 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
14543 * _e32 for 32-bit VOP1/VOP2/VOPC
14548 VOP1/VOP2/VOP3/VOPC examples:
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 29 field bit VOP2 = 0;
167 let TSFlags{8} = VOP2;
242 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
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| D | VOP2Instructions.td | 10 // VOP2 Classes
76 let VOP2 = 1;
89 let VOP2 = 1;
695 // VOP2 Instructions
1239 //===------------------------------- VOP2 -------------------------------===//
1281 //===------------------------- VOP2 (with name) -------------------------===//
1510 //===------------------------------- VOP2 -------------------------------===//
1556 //===------------------------- VOP2 (with name) -------------------------===//
1784 // VOP2 no carry-in, carry-out.
1792 // VOP2 carry-in, carry-out.
[all …]
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| D | SIDefines.h | 41 VOP2 = 1 << 8, enumerator
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| D | SIInstrInfo.h | 435 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
439 return get(Opcode).TSFlags & SIInstrFlags::VOP2; in isVOP2()
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| D | VOP3Instructions.td | 923 defm V_READLANE_B32 : VOP3_Real_No_Suffix_gfx11<0x360>; // Pseudo in VOP2
925 defm V_WRITELANE_B32 : VOP3_Real_No_Suffix_gfx11<0x361>; // Pseudo in VOP2
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| D | VOPInstructions.td | 1442 // VOP1 and VOP2 depend on these triple defs
1515 def VOP2InfoTable : VOPInfoTable<"VOP2">;
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| D | SIInstrInfo.td | 1616 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
1846 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1886 // VOP2 without modifiers
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| D | SIInstructions.td | 1042 // VOP2 Patterns
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| /openbsd/src/gnu/llvm/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX1011.rst | 56 VOP2 section in Instructions
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| D | AMDGPUAsmGFX906.rst | 36 VOP2 section in Instructions
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| D | AMDGPUAsmGFX908.rst | 56 VOP2 section in Instructions
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| D | AMDGPUAsmGFX7.rst | 719 VOP2 section in Instructions
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| D | AMDGPUAsmGFX11.rst | 1301 VOP2 section in Instructions
1359 VOP2 DPP16
1410 VOP2 DPP8
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| D | AMDGPUAsmGFX8.rst | 866 VOP2 section in Instructions
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| D | AMDGPUAsmGFX90a.rst | 964 VOP2 section in Instructions
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| D | AMDGPUAsmGFX9.rst | 1054 VOP2 section in Instructions
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| D | AMDGPUAsmGFX940.rst | 960 VOP2 section in Instructions
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| D | AMDGPUAsmGFX1030.rst | 1345 VOP2 section in Instructions
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| D | AMDGPUAsmGFX10.rst | 1436 VOP2 section in Instructions
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3474 (SIInstrFlags::VOPC | SIInstrFlags::VOP1 | SIInstrFlags::VOP2 | in validateConstantBusLimitations()
4068 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
8934 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2); in cvtSdwaVOP2()
8938 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true); in cvtSdwaVOP2b()
8942 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true); in cvtSdwaVOP2e()
8974 if (BasicInstType == SIInstrFlags::VOP2 && in cvtSDWA()
9022 case SIInstrFlags::VOP2: in cvtSDWA()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 380 ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) in printVOPDst()
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