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Searched refs:WR_CONFIRM (Results 1 – 13 of 13) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dsoc15d.h125 #define WR_CONFIRM (1 << 20) macro
Dnvd.h98 #define WR_CONFIRM (1 << 20) macro
Dvid.h151 #define WR_CONFIRM (1 << 20) macro
Dcikd.h269 #define WR_CONFIRM (1 << 20) macro
Dgfx_v9_4_3.c386 (wc ? WR_CONFIRM : 0)); in gfx_v9_4_3_write_data_to_reg()
479 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()
2985 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
2994 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
3029 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_4_3_ring_emit_wreg()
3035 cmd = WR_CONFIRM; in gfx_v9_4_3_ring_emit_wreg()
Dgfx_v9_0.c1139 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()
1221 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()
5645 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5654 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
5694 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()
5807 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()
5902 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
5908 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
Dgfx_v11_0.c456 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
590 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()
5774 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5783 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5879 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()
6006 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()
6052 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
6058 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
Dgfx_v8_0.c892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()
6280 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6289 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6375 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
6381 cmd = WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
7259 WR_CONFIRM) | in gfx_v8_0_ring_emit_ce_meta()
7292 WR_CONFIRM) | in gfx_v8_0_ring_emit_de_meta()
Dgfx_v12_0.c492 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()
4451 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
4460 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
4589 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()
4595 cmd = WR_CONFIRM; in gfx_v12_0_ring_emit_wreg()
Dgfx_v10_0.c3917 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()
4010 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()
8683 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8692 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()
8820 WR_CONFIRM) | in gfx_v10_0_ring_emit_ce_meta()
8856 WR_CONFIRM) | in gfx_v10_0_ring_emit_de_meta()
8902 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
8908 cmd = WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
Dsid.h1709 #define WR_CONFIRM (1 << 20) macro
/openbsd/src/sys/dev/pci/drm/radeon/
Dsid.h1646 #define WR_CONFIRM (1 << 20) macro
Dcikd.h1737 #define WR_CONFIRM (1 << 20) macro