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/openbsd/src/sys/dev/ic/
Dathvar.h341 #define ATH_LOCK_INIT(_sc) \ argument
342 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
344 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
345 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
346 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
347 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
349 #define ATH_TXBUF_LOCK_INIT(_sc) \ argument
350 mtx_init(&(_sc)->sc_txbuflock, \
351 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
352 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) argument
[all …]
Dgemvar.h213 #define GEM_DMA_READ(_sc, _a) \ argument
214 (((_sc)->sc_pci) ? lemtoh64(_a) : bemtoh64(_a))
215 #define GEM_DMA_WRITE(_sc, _a, _v) \ argument
216 (((_sc)->sc_pci) ? htolem64((_a), (_v)) : htobem64((_a), (_v)))
Dsilivar.h39 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dqlwvar.h145 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dqlavar.h192 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dnvmevar.h138 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dqla.c166 #define qla_queue_read(_sc, _r) ((*(_sc)->sc_regs->read)((_sc), (_r))) argument
167 #define qla_queue_write(_sc, _r, _v) qla_write((_sc), (_r), (_v)) argument
169 #define qla_read_isr(_sc, _isr, _info) \ argument
170 ((*(_sc)->sc_regs->read_isr)((_sc), (_isr), (_info)))
/openbsd/src/sys/dev/pci/
Dif_stgereg.h47 #define CSR_WRITE_4(_sc, reg, val) \ argument
48 bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
49 #define CSR_WRITE_2(_sc, reg, val) \ argument
50 bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
51 #define CSR_WRITE_1(_sc, reg, val) \ argument
52 bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
54 #define CSR_READ_4(_sc, reg) \ argument
55 bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))
56 #define CSR_READ_2(_sc, reg) \ argument
57 bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))
[all …]
Dif_jmevar.h223 #define CSR_WRITE_4(_sc, reg, val) \ argument
224 bus_space_write_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg), (val))
225 #define CSR_READ_4(_sc, reg) \ argument
226 bus_space_read_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg))
230 #define JME_RXCHAIN_RESET(_sc) \ argument
232 (_sc)->jme_cdata.jme_rxhead = NULL; \
233 (_sc)->jme_cdata.jme_rxtail = NULL; \
234 (_sc)->jme_cdata.jme_rxlen = 0; \
Dif_em.h377 #define FOREACH_QUEUE(_sc, _que) \ argument
378 for ((_que) = (_sc)->queues; \
379 (_que) < ((_sc)->queues + (_sc)->num_queues); \
461 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dif_agereg.h873 #define AGE_COMMIT_MBOX(_sc) \ argument
875 CSR_WRITE_4(_sc, AGE_MBOX, \
876 (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \
878 (((_sc)->age_cdata.age_rr_cons << \
880 (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \
884 #define AGE_RXCHAIN_RESET(_sc) \ argument
886 (_sc)->age_cdata.age_rxhead = NULL; \
887 (_sc)->age_cdata.age_rxtail = NULL; \
888 (_sc)->age_cdata.age_rxprev_tail = NULL; \
889 (_sc)->age_cdata.age_rxlen = 0; \
Dif_alcreg.h1473 #define CSR_WRITE_4(_sc, reg, val) \ argument
1475 #define CSR_WRITE_2(_sc, reg, val) \ argument
1477 #define CSR_WRITE_1(_sc, reg, val) \ argument
1479 #define CSR_READ_2(_sc, reg) \ argument
1481 #define CSR_READ_4(_sc, reg) \ argument
1484 #define ALC_RXCHAIN_RESET(_sc) \ argument
1486 (_sc)->alc_cdata.alc_rxhead = NULL; \
1487 (_sc)->alc_cdata.alc_rxtail = NULL; \
1488 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \
1489 (_sc)->alc_cdata.alc_rxlen = 0; \
Dif_alereg.h947 #define CSR_WRITE_4(_sc, reg, val) \ argument
949 #define CSR_WRITE_2(_sc, reg, val) \ argument
951 #define CSR_WRITE_1(_sc, reg, val) \ argument
953 #define CSR_READ_2(_sc, reg) \ argument
955 #define CSR_READ_4(_sc, reg) \ argument
Dif_vic.c241 #define VIC_TXURN_WARN(_sc) ((_sc)->sc_txpending >= ((_sc)->sc_ntxbuf - 5)) argument
242 #define VIC_TXURN(_sc) ((_sc)->sc_txpending >= (_sc)->sc_ntxbuf) argument
282 #define VIC_DMA_DVA(_sc) ((_sc)->sc_dma_map->dm_segs[0].ds_addr) argument
283 #define VIC_DMA_KVA(_sc) ((void *)(_sc)->sc_dma_kva) argument
Dif_igc.h331 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dif_vtereg.h450 #define CSR_WRITE_2(_sc, reg, val) \ argument
452 #define CSR_READ_2(_sc, reg) \ argument
Dif_bnxt.c102 #define BNXT_HWRM_LOCK_INIT(_sc, _name) \ argument
104 #define BNXT_HWRM_LOCK(_sc) mtx_enter(&_sc->sc_lock) argument
105 #define BNXT_HWRM_UNLOCK(_sc) mtx_leave(&_sc->sc_lock) argument
106 #define BNXT_HWRM_LOCK_DESTROY(_sc) /* nothing */ argument
107 #define BNXT_HWRM_LOCK_ASSERT(_sc) MUTEX_ASSERT_LOCKED(&_sc->sc_lock) argument
267 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dif_ngbereg.h1069 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
/openbsd/src/sys/net/
Dtrunklacp.h284 #define LACP_SOFTC(_sc) ((struct lacp_softc *)(_sc)->tr_psc) argument
Dif_wg.c1532 wg_handshake_worker(void *_sc) in wg_handshake_worker() argument
1535 struct wg_softc *sc = _sc; in wg_handshake_worker()
1777 wg_encap_worker(void *_sc) in wg_encap_worker() argument
1780 struct wg_softc *sc = _sc; in wg_encap_worker()
1786 wg_decap_worker(void *_sc) in wg_decap_worker() argument
1789 struct wg_softc *sc = _sc; in wg_decap_worker()
1997 wg_remote_get(void *_sc, uint8_t public[NOISE_PUBLIC_KEY_LEN]) in wg_remote_get() argument
2000 struct wg_softc *sc = _sc; in wg_remote_get()
2007 wg_index_set(void *_sc, struct noise_remote *remote) in wg_index_set() argument
2010 struct wg_softc *sc = _sc; in wg_index_set()
[all …]
Dif_tpmr.c99 #define DPRINTF(_sc, fmt...) do { \ argument
100 if (ISSET((_sc)->sc_if.if_flags, IFF_DEBUG)) \
/openbsd/src/sys/dev/usb/
Durng.c40 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Duonerng.c98 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
Dumcs.c64 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument
/openbsd/src/sys/dev/fdt/
Drkusbphy.c181 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) argument

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