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Searched refs:isSGPRReg (Results 1 – 13 of 13) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIOptimizeExecMasking.cpp627 if (!TRI->isSGPRReg(*MRI, SaveExecDest)) in tryRecordVCmpxAndSaveexecSequence()
659 if (Src0->isReg() && TRI->isSGPRReg(*MRI, Src0->getReg()) && in tryRecordVCmpxAndSaveexecSequence()
664 if (Src1->isReg() && TRI->isSGPRReg(*MRI, Src1->getReg()) && in tryRecordVCmpxAndSaveexecSequence()
DSIFixSGPRCopies.cpp703 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && in runOnMachineFunction()
705 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && in runOnMachineFunction()
932 if (TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst)) in analyzeVGPRToSGPRCopy()
DSIRegisterInfo.h195 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
DSIFoldOperands.cpp766 if (TRI->isSGPRReg(*MRI, Src.Reg)) { in foldOperand()
837 if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) { in foldOperand()
1055 bool IsSGPR = TRI->isSGPRReg(*MRI, MI->getOperand(0).getReg()); in tryConstantFoldOp()
DGCNHazardRecognizer.cpp966 if (TRI->isSGPRReg(MRI, UseReg)) { in checkVALUHazards()
1055 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg())) in checkRWLaneHazards()
2812 if (TRI.isSGPRReg(MRI, OpReg)) in fixVALUMaskWriteHazard()
DSILowerI1Copies.cpp97 return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) && in isLaneMaskReg()
DSIInstrInfo.cpp3485 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) { in convertToThreeAddress()
3708 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg())) in mayReadEXEC()
4785 if (Src->isReg() && RI.isSGPRReg(MRI, Src->getReg())) { in verifyInstruction()
5172 RI.isSGPRReg(MRI, MO->getReg())) in isOperandLegal()
5203 RI.isSGPRReg(MRI, Src0.getReg())) in legalizeOperandsVOP2()
5462 if (RI.isSGPRReg(MRI, SAddr.getReg())) in moveFlatAddrToVGPR()
7053 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) { in splitScalar64BitXnor()
DSIInstrInfo.h797 return !RI.isSGPRReg(MRI, Dest); in isVGPRCopy()
DSIPeepholeSDWA.cpp1167 TRI->isSGPRReg(*MRI, Op.getReg())) { in legalizeScalarOperands()
DAMDGPUCallLowering.cpp72 if (TRI->isSGPRReg(MRI, PhysReg)) { in assignValueToReg()
DSIInsertWaitcnts.cpp511 } else if (TRI->isSGPRReg(*MRI, Op.getReg())) { in getRegInterval()
DSIRegisterInfo.cpp2779 bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI, in isSGPRReg() function in SIRegisterInfo
DSIISelLowering.cpp12132 !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg())) in AdjustInstrPostInstrSelection()
12774 return !TRI->isSGPRReg(MRI, Reg); in isSDNodeSourceOfDivergence()
12780 return !TRI->isSGPRReg(MRI, Reg); in isSDNodeSourceOfDivergence()