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Searched refs:isShiftedInt (Results 1 – 17 of 17) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonDepOperands.td18 defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
21 defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
30 defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
33 defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
36 defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
39 defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
42 defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
45 defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
48 defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
51 defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
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DHexagonInstrInfo.cpp2913 return isShiftedInt<11,1>(Offset); in isValidOffset()
2917 return isShiftedInt<11,2>(Offset); in isValidOffset()
4080 isShiftedInt<6,3>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
DHexagonPatterns.td2638 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVInstrInfoZicbo.td20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
27 return isShiftedInt<7, 5>(Imm);
DRISCVInstrInfoC.td155 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
163 return isShiftedInt<8, 1>(Imm);
203 [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
213 return isShiftedInt<6, 4>(Imm) && (Imm != 0);
219 ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
227 return isShiftedInt<11, 1>(Imm);
DRISCVInstrInfoZb.td218 return !isInt<13>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 2>(C);
227 return !isInt<14>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 3>(C);
DRISCVInstrInfo.cpp1636 Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0); in verifyInstruction()
1663 Ok = isShiftedInt<7, 5>(Imm); in verifyInstruction()
DRISCVInstrInfo.td264 return isShiftedInt<12, 1>(Imm);
303 return isShiftedInt<20, 1>(Imm);
/openbsd/src/gnu/llvm/llvm/include/llvm/ExecutionEngine/JITLink/
Dloongarch.h199 if (!isShiftedInt<26, 2>(Value)) in applyFixup()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.h209 return isShiftedInt<N, S>(minConstant(MCI, Index)); in inSRange()
DHexagonMCDuplexInfo.cpp546 if (!isShiftedInt<7, 0>(Value)) in subInstWouldBeExtended()
/openbsd/src/gnu/llvm/lld/MachO/Arch/
DARM64.cpp267 return ldr.p2Size > 1 && isShiftedInt<19, 2>(ldr.offset); in isLiteralLdrEligible()
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMathExtras.h226 constexpr inline bool isShiftedInt(int64_t x) { in isShiftedInt() function
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp391 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
698 return IsConstantImm && isShiftedInt<7, 5>(Imm) && in isSImm12Lsb00000()
710 return IsConstantImm && (Imm != 0) && isShiftedInt<6, 4>(Imm) && in isSImm10Lsb0000NonZero()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
DAArch64LegalizerInfo.cpp1165 isShiftedInt<7, 3>(NewOffset)) { in matchLDPSTPAddrMode()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1354 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1358 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
1405 isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) in isScaledSImm()
1413 return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); in isScaledSImm()
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp16420 if (isShiftedInt<16, 16>(Value)) in LowerAsmOperandForConstraint()