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Searched refs:nxv2f64 (Results 1 – 18 of 18) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DSVEInstrFormats.td1260 …def : Pat<(nxv2f64 (splat_vector (f64 (vector_extract (nxv2f64 ZPR:$vec), sve_elm_idx_extdup_d:$in…
1275 def : Pat<(nxv2f64 (AArch64duplane128 nxv2f64:$Op1, i64:$imm)),
1323 def : SVE_2_Op_Pat<nxv2f64, op, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
1364 def : Pat<(nxv2f64 (op nxv2f64:$Op1, nxv2f64:$Op2, nxv2i64:$Op3)),
1365 (nxv2f64 (!cast<Instruction>(NAME # _D) (REG_SEQUENCE ZPR2, nxv2f64:$Op1, zsub0,
1366 nxv2f64:$Op2, zsub1),
1409 def : SVE_3_Op_Pat<nxv2f64, op, nxv2f64, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
1444 def : SVE_1_Op_Pat<nxv2f64, op, nxv2f64, !cast<Instruction>(NAME # _D)>;
1565 def : Pat<(nxv2f64 (op nxv2f64:$Zn, f64:$Vm)),
1667 def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
[all …]
DAArch64SVEInstrInfo.td706 defm : fma<nxv2f64, nxv2i1, "D">;
762 def : Pat<(nxv2f64 (splat_vector (f64 FPR64:$src))),
777 def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (DUP_ZI_D 0, 0)>;
803 def : Pat<(nxv2f64 (splat_vector (f64 fpimm:$val))),
818 def : Pat<(nxv2f64 (splat_vector fpimm64:$imm8)),
1241 defm : sve_masked_gather_x2_scaled<nxv2f64, nonext_masked_gather_signed_scaled, "GLD1D">;
1253 …defm : sve_masked_gather_x2_unscaled<nxv2f64, nonext_masked_gather_signed_unscaled, "GLD1D", …
1430 defm : sve_masked_scatter_x2_scaled<nxv2f64, nontrunc_masked_scatter_signed_scaled, "SST1D">;
1439 …defm : sve_masked_scatter_x2_unscaled<nxv2f64, nontrunc_masked_scatter_signed_unscaled, "SST1D",…
2090 …4, ZPR16, int_aarch64_sve_fcvt_f16f64, AArch64fcvtr_mt, nxv2f16, nxv2i1, nxv2f64, ElementSizeD>;
[all …]
DAArch64SMEInstrInfo.td780 … : sme2_multi_vec_array_vg2_index_64b<"fmla", 0b00, ZZ_d_mul_r, ZPR4b64, nxv2f64, int_aarch64_sme_…
781 …sme2_multi_vec_array_vg4_index_64b<"fmla", 0b000, ZZZZ_d_mul_r, ZPR4b64, nxv2f64, int_aarch64_sme_…
782 …a_add_sub_array_vg2_single<"fmla", 0b1011000, MatrixOp64, ZZ_d, ZPR4b64, nxv2f64, int_aarch64_sme_…
783 …add_sub_array_vg4_single<"fmla", 0b1111000, MatrixOp64, ZZZZ_d, ZPR4b64, nxv2f64, int_aarch64_sme_…
784 …ot_mla_add_sub_array_vg2_multi<"fmla", 0b111000, MatrixOp64, ZZ_d_mul_r, nxv2f64, int_aarch64_sme_…
785 …_mla_add_sub_array_vg4_multi<"fmla", 0b111000, MatrixOp64, ZZZZ_d_mul_r, nxv2f64, int_aarch64_sme_…
787 … : sme2_multi_vec_array_vg2_index_64b<"fmls", 0b10, ZZ_d_mul_r, ZPR4b64, nxv2f64, int_aarch64_sme_…
788 …sme2_multi_vec_array_vg4_index_64b<"fmls", 0b010, ZZZZ_d_mul_r, ZPR4b64, nxv2f64, int_aarch64_sme_…
789 …a_add_sub_array_vg2_single<"fmls", 0b1011001, MatrixOp64, ZZ_d, ZPR4b64, nxv2f64, int_aarch64_sme_…
790 …add_sub_array_vg4_single<"fmls", 0b1111001, MatrixOp64, ZZZZ_d, ZPR4b64, nxv2f64, int_aarch64_sme_…
[all …]
DAArch64TargetTransformInfo.cpp1967 { ISD::FP_TO_SINT, MVT::nxv2i64, MVT::nxv2f64, 1 }, in getCastInstrCost()
1968 { ISD::FP_TO_SINT, MVT::nxv2i32, MVT::nxv2f64, 1 }, in getCastInstrCost()
1969 { ISD::FP_TO_SINT, MVT::nxv2i16, MVT::nxv2f64, 1 }, in getCastInstrCost()
1970 { ISD::FP_TO_SINT, MVT::nxv2i8, MVT::nxv2f64, 1 }, in getCastInstrCost()
1971 { ISD::FP_TO_UINT, MVT::nxv2i64, MVT::nxv2f64, 1 }, in getCastInstrCost()
1972 { ISD::FP_TO_UINT, MVT::nxv2i32, MVT::nxv2f64, 1 }, in getCastInstrCost()
1973 { ISD::FP_TO_UINT, MVT::nxv2i16, MVT::nxv2f64, 1 }, in getCastInstrCost()
1974 { ISD::FP_TO_UINT, MVT::nxv2i8, MVT::nxv2f64, 1 }, in getCastInstrCost()
2042 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 }, in getCastInstrCost()
2047 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 }, in getCastInstrCost()
[all …]
DAArch64CallingConvention.td79 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],
82 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],
149 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],
179 nxv2bf16, nxv4bf16, nxv8bf16, nxv2f32, nxv4f32, nxv2f64],
DAArch64ISelDAGToDAG.cpp4584 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
4605 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
4626 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
5034 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
5051 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
5068 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
5678 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
5695 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
5712 } else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) { in Select()
DSMEInstrFormats.td192 (nxv2f64 ZPR64:$zn), (nxv2f64 ZPR64:$zm)),
917 nxv2f64, nxv2i1, sme_elm_idx0_7, sme_elm_idx0_1,
945 nxv2f64, nxv2i1, sme_elm_idx0_15,
1084 nxv2f64, nxv2i1, sme_elm_idx0_1,
1112 nxv2f64, nxv2i1, sme_elm_idx0_0,
DAArch64RegisterInfo.td1054 nxv2f64],
DAArch64ISelLowering.cpp160 return MVT::nxv2f64; in getPackedSVEVectorVT()
387 addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass); in AArch64TargetLowering()
1362 MVT::nxv4f32, MVT::nxv2f64}) { in AArch64TargetLowering()
9783 (VT == MVT::nxv8f16 || VT == MVT::nxv4f32 || VT == MVT::nxv2f64))) { in getEstimate()
18474 case MVT::nxv2f64: in getSVEContainerType()
20844 if ((SrcVT != MVT::nxv4f32) && (SrcVT != MVT::nxv2f64)) in performScatterStoreCombine()
22856 return EVT(MVT::nxv2f64); in getContainerForFixedLengthVector()
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h267 nxv2f64 = 185, // n x 2 x f64 enumerator
715 case nxv2f64: in getVectorElementType()
879 case nxv2f64: return 2; in getVectorMinNumElements()
1027 case nxv2f64: return TypeSize::Scalable(128); in getSizeInBits()
1486 if (NumElements == 2) return MVT::nxv2f64; in getScalableVectorVT()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVTargetTransformInfo.cpp385 {Intrinsic::floor, MVT::nxv2f64, 9},
402 {Intrinsic::ceil, MVT::nxv2f64, 9},
419 {Intrinsic::trunc, MVT::nxv2f64, 7},
436 {Intrinsic::round, MVT::nxv2f64, 9},
453 {Intrinsic::roundeven, MVT::nxv2f64, 9},
DRISCVRegisterInfo.td277 // double* N/A N/A N/A nxv1f64 nxv2f64 nxv4f64 nxv8f64
322 defvar vfloat64m2_t = nxv2f64;
DRISCVISelLowering.cpp131 MVT::nxv1f64, MVT::nxv2f64, MVT::nxv4f64, MVT::nxv8f64}; in RISCVTargetLowering()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DValueTypes.td227 def nxv2f64 : ValueType<128, 185>; // n x 2 x f64 vector value
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DValueTypes.cpp549 case MVT::nxv2f64: in getTypeForEVT()
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenTarget.cpp251 case MVT::nxv2f64: return "MVT::nxv2f64"; in getEnumName()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsicsAArch64.td953 def llvm_nxv2f64_ty : LLVMType<nxv2f64>;
/openbsd/src/gnu/llvm/llvm/docs/
DLangRef.rst17574 …declare <vscale x 2 x double> @llvm.vector.insert.nxv2f64.v2f64(<vscale x 2 x double> %vec, <2 x d…
17577 …declare <vscale x 4 x float> @llvm.vector.insert.nxv4f64.nxv2f64(<vscale x 4 x float> %vec, <vscal…
17620 declare <2 x double> @llvm.vector.extract.v2f64.nxv2f64(<vscale x 2 x double> %vec, i64 <idx>)