| /openbsd/src/sys/dev/pci/drm/i915/display/ |
| D | intel_color_regs.h | 33 #define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ argument
34 _PICK_EVEN_2RANGES(pipe, 2, \
42 #define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ argument
48 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) argument
65 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) argument
69 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) /* u1… argument
73 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) argument
120 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_G… argument
121 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) argument
122 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_G… argument
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| D | intel_pipe_crc_regs.h | 12 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) argument
63 #define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A) argument
67 #define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A) argument
71 #define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I9… argument
75 #define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X) argument
79 #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) argument
82 #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) argument
85 #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) argument
88 #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_… argument
91 #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A… argument
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| D | intel_display_irq.c | 28 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
30 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_handle_vblank()
110 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
122 new_val = dev_priv->display.irq.de_irq_mask[pipe]; in bdw_update_pipe_irq()
126 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { in bdw_update_pipe_irq()
127 dev_priv->display.irq.de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
128 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), in bdw_update_pipe_irq()
129 dev_priv->display.irq.de_irq_mask[pipe]); in bdw_update_pipe_irq()
130 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
135 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
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| D | intel_pch_display.c | 22 enum pipe pch_transcoder) in intel_has_pch_trancoder()
28 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) in intel_crtc_pch_transcoder()
35 return crtc->pipe; in intel_crtc_pch_transcoder()
39 enum pipe pipe, enum port port, in assert_pch_dp_disabled() argument
42 enum pipe port_pipe; in assert_pch_dp_disabled()
47 I915_STATE_WARN(dev_priv, state && port_pipe == pipe, in assert_pch_dp_disabled()
49 port_name(port), pipe_name(pipe)); in assert_pch_dp_disabled()
58 enum pipe pipe, enum port port, in assert_pch_hdmi_disabled() argument
61 enum pipe port_pipe; in assert_pch_hdmi_disabled()
66 I915_STATE_WARN(dev_priv, state && port_pipe == pipe, in assert_pch_hdmi_disabled()
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| D | intel_sprite_regs.h | 12 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) argument
37 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) argument
41 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) argument
45 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) argument
53 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) argument
61 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) argument
65 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) argument
69 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) argument
74 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) argument
78 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) argument
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| D | intel_vdsc_regs.h | 31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
60 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
63 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
66 #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ argument
69 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ argument
72 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) argument
73 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) argument
202 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
205 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
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| D | intel_fifo_underrun.c | 62 enum pipe pipe; in ivb_can_enable_err_int() local
66 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
67 crtc = intel_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
79 enum pipe pipe; in cpt_can_enable_serr_int() local
84 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
97 i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
105 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
109 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
110 drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
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| D | intel_dsb_regs.h | 13 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ argument
14 (pipe) * 0x1000 + (id) * 0x100)
15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) argument
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) argument
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) argument
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc) argument
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10) argument
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) argument
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) argument
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) argument
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| D | skl_universal_plane_regs.h | 11 #define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
12 _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
13 #define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
14 (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
15 #define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
16 _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
17 #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
18 _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
20 #define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_… argument
22 _PIPE((pipe), (reg_1_a), (reg_1_b)), \
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| D | intel_cursor_regs.h | 12 #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) argument
28 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) argument
44 #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE) argument
47 #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS) argument
56 #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT) argument
59 #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE) argument
66 #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A) argument
72 #define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A) argument
75 #define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE) argument
80 #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4) argument
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| D | intel_fdi.c | 27 enum pipe pipe, bool state) in assert_fdi_tx() argument
38 enum transcoder cpu_transcoder = (enum transcoder)pipe; in assert_fdi_tx()
42 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
49 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_tx_enabled() argument
51 assert_fdi_tx(i915, pipe, true); in assert_fdi_tx_enabled()
54 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_tx_disabled() argument
56 assert_fdi_tx(i915, pipe, false); in assert_fdi_tx_disabled()
60 enum pipe pipe, bool state) in assert_fdi_rx() argument
64 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
70 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_rx_enabled() argument
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| D | intel_audio_regs.h | 20 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ argument
24 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ argument
35 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) argument
38 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) argument
43 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) argument
46 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) argument
51 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) argument
54 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) argument
57 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) argument
137 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) argument
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| D | intel_link_bw.c | 30 enum pipe pipe; in intel_link_bw_init_limits() local
34 for_each_pipe(display, pipe) { in intel_link_bw_init_limits()
37 intel_crtc_for_pipe(i915, pipe)); in intel_link_bw_init_limits()
40 limits->max_bpp_x16[pipe] = crtc_state->max_link_bpp_x16; in intel_link_bw_init_limits()
42 limits->force_fec_pipes |= BIT(pipe); in intel_link_bw_init_limits()
44 limits->max_bpp_x16[pipe] = INT_MAX; in intel_link_bw_init_limits()
74 enum pipe max_bpp_pipe = INVALID_PIPE; in intel_link_bw_reduce_bpp()
82 if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe)) in intel_link_bw_reduce_bpp()
103 max_bpp_pipe = crtc->pipe; in intel_link_bw_reduce_bpp()
138 enum pipe pipe) in intel_link_bw_set_bpp_limit_for_pipe() argument
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| D | intel_sprite.c | 51 static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite) in sprite_name() argument
53 return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A'; in sprite_name()
144 enum pipe pipe = plane->pipe; in vlv_sprite_update_clrc() local
171 intel_de_write_fw(display, SPCLRC0(pipe, plane_id), in vlv_sprite_update_clrc()
173 intel_de_write_fw(display, SPCLRC1(pipe, plane_id), in vlv_sprite_update_clrc()
362 enum pipe pipe = plane->pipe; in vlv_sprite_update_gamma() local
376 intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1), in vlv_sprite_update_gamma()
386 enum pipe pipe = plane->pipe; in vlv_sprite_update_noarm() local
393 intel_de_write_fw(display, SPSTRIDE(pipe, plane_id), in vlv_sprite_update_noarm()
395 intel_de_write_fw(display, SPPOS(pipe, plane_id), in vlv_sprite_update_noarm()
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| D | intel_fdi.h | 11 enum pipe;
40 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe);
41 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe);
42 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe);
43 void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe);
44 void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
45 void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
46 void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
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| D | intel_pipe_crc.c | 77 enum pipe pipe, in i9xx_pipe_crc_auto_source() argument
93 if (crtc->pipe != pipe) in i9xx_pipe_crc_auto_source()
127 enum pipe pipe, in vlv_pipe_crc_ctl_reg() argument
134 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in vlv_pipe_crc_ctl_reg()
174 switch (pipe) { in vlv_pipe_crc_ctl_reg()
194 enum pipe pipe, in i9xx_pipe_crc_ctl_reg() argument
199 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in i9xx_pipe_crc_ctl_reg()
231 enum pipe pipe) in vlv_undo_pipe_scramble_reset() argument
235 switch (pipe) { in vlv_undo_pipe_scramble_reset()
310 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
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| D | intel_color.c | 212 enum pipe pipe = crtc->pipe; in ilk_update_pipe_csc() local
214 intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), csc->preoff[0]); in ilk_update_pipe_csc()
215 intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), csc->preoff[1]); in ilk_update_pipe_csc()
216 intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), csc->preoff[2]); in ilk_update_pipe_csc()
218 intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
220 intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe), in ilk_update_pipe_csc()
223 intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
225 intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe), in ilk_update_pipe_csc()
228 intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
230 intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe), in ilk_update_pipe_csc()
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| D | skl_universal_plane.c | 601 enum pipe pipe = plane->pipe; in icl_program_input_csc() local
644 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), in icl_program_input_csc()
646 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), in icl_program_input_csc()
648 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), in icl_program_input_csc()
650 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), in icl_program_input_csc()
652 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), in icl_program_input_csc()
654 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), in icl_program_input_csc()
657 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), in icl_program_input_csc()
659 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), in icl_program_input_csc()
661 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), in icl_program_input_csc()
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| D | intel_fdi_regs.h | 28 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) argument
33 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) argument
83 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) argument
119 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) argument
125 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) argument
126 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) argument
145 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) argument
146 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) argument
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| D | intel_dpll.h | 17 enum pipe;
31 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
33 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
36 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
38 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
49 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
50 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
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| /openbsd/src/sys/dev/pci/drm/ |
| D | drm_vblank.c | 157 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
170 drm_vblank_crtc(struct drm_device *dev, unsigned int pipe) in drm_vblank_crtc() argument
172 return &dev->vblank[pipe]; in drm_vblank_crtc()
182 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank() argument
186 struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe); in store_vblank()
198 static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe) in drm_max_vblank_count() argument
200 struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe); in drm_max_vblank_count()
209 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter() argument
211 drm_WARN_ON_ONCE(dev, drm_max_vblank_count(dev, pipe) != 0); in drm_vblank_no_hw_counter()
215 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter() argument
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| /openbsd/src/gnu/usr.bin/perl/dist/IO/t/ |
| D | io_pipe.t | 40 my $pipe;
45 $pipe = IO::Pipe->new()->reader($perl, '-e', 'print qq(not ok 1\n)');
46 while (<$pipe>) {
50 $pipe->close or print "# \$!=$!\nnot ";
53 $pipe = IO::Pipe->new()->writer($perl, '-pe', $cmd);
54 print $pipe "not ok 3\n" ;
55 $pipe->close or print "# \$!=$!\nnot ";
66 $pipe = IO::Pipe->new();
72 $pipe->writer;
73 print $pipe "Xk 5\n";
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| /openbsd/src/sys/dev/usb/ |
| D | usbdi.c | 57 void usbd_start_next(struct usbd_pipe *pipe);
148 usbd_dump_queue(struct usbd_pipe *pipe) in usbd_dump_queue() argument
152 printf("%s: pipe=%p\n", __func__, pipe); in usbd_dump_queue()
153 SIMPLEQ_FOREACH(xfer, &pipe->queue, next) { in usbd_dump_queue()
159 usbd_dump_pipe(struct usbd_pipe *pipe) in usbd_dump_pipe() argument
161 printf("%s: pipe=%p\n", __func__, pipe); in usbd_dump_pipe()
162 if (pipe == NULL) in usbd_dump_pipe()
164 usbd_dump_iface(pipe->iface); in usbd_dump_pipe()
165 usbd_dump_device(pipe->device); in usbd_dump_pipe()
166 usbd_dump_endpoint(pipe->endpoint); in usbd_dump_pipe()
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| /openbsd/src/sys/dev/pci/drm/i915/ |
| D | vlv_sideband_reg.h | 49 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
50 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
51 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
52 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) argument
53 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) argument
54 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) argument
55 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) argument
56 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) argument
57 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) argument
58 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) argument
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| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | mes_v12_0.c | 145 int pipe, void *pkt, int size, in mes_v12_0_submit_pkt_and_poll_completion() argument
151 struct amdgpu_ring *ring = &mes->ring[pipe]; in mes_v12_0_submit_pkt_and_poll_completion()
152 spinlock_t *ring_lock = &mes->ring_lock[pipe]; in mes_v12_0_submit_pkt_and_poll_completion()
218 pipe, op_str, misc_op_str); in mes_v12_0_submit_pkt_and_poll_completion()
221 pipe, op_str); in mes_v12_0_submit_pkt_and_poll_completion()
224 pipe, x_pkt->header.opcode); in mes_v12_0_submit_pkt_and_poll_completion()
231 pipe, op_str, misc_op_str); in mes_v12_0_submit_pkt_and_poll_completion()
234 pipe, op_str); in mes_v12_0_submit_pkt_and_poll_completion()
237 pipe, x_pkt->header.opcode); in mes_v12_0_submit_pkt_and_poll_completion()
357 int pipe; in mes_v12_0_reset_hw_queue() local
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