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Searched refs:regCP_PFP_IC_BASE_CNTL (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v11_0.c2376 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache()
2381 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2451 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2455 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
3061 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3065 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
Dgfx_v12_0.c2274 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2278 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_offset.h8395 #define regCP_PFP_IC_BASE_CNTL … macro
Dgc_12_0_0_offset.h6200 #define regCP_PFP_IC_BASE_CNTL … macro
Dgc_11_0_3_offset.h10274 #define regCP_PFP_IC_BASE_CNTL … macro
Dgc_11_0_0_offset.h9724 #define regCP_PFP_IC_BASE_CNTL … macro