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Searched refs:regRLC_UTCL1_STATUS (Results 1 – 8 of 8) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_4_3_offset.h6720 #define regRLC_UTCL1_STATUS … macro
Dgc_9_4_2_offset.h5198 #define regRLC_UTCL1_STATUS … macro
Dgc_11_5_0_offset.h8719 #define regRLC_UTCL1_STATUS … macro
Dgc_12_0_0_offset.h6548 #define regRLC_UTCL1_STATUS … macro
Dgc_11_0_3_offset.h10656 #define regRLC_UTCL1_STATUS … macro
Dgc_11_0_0_offset.h10054 #define regRLC_UTCL1_STATUS … macro
/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_3.c86 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
Dgfx_v11_0.c143 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),