Home
last modified time | relevance | path

Searched refs:regmap_read_4 (Results 1 – 25 of 30) sorted by relevance

12

/openbsd/src/sys/arch/riscv64/dev/
Dstfclock.c673 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF); in stfclock_get_frequency_jh7110_pll()
677 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF); in stfclock_get_frequency_jh7110_pll()
680 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF); in stfclock_get_frequency_jh7110_pll()
684 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PREDIV_OFF); in stfclock_get_frequency_jh7110_pll()
690 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_PD_OFF); in stfclock_get_frequency_jh7110_pll()
695 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_FRAC_OFF); in stfclock_get_frequency_jh7110_pll()
699 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL_PREDIV_OFF); in stfclock_get_frequency_jh7110_pll()
755 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_PD_OFF); in stfclock_set_frequency_jh7110_pll()
759 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FBDIV_OFF); in stfclock_set_frequency_jh7110_pll()
762 reg = regmap_read_4(sc->sc_rm, base + JH7110_PLL0_FRAC_OFF); in stfclock_set_frequency_jh7110_pll()
[all …]
Dstfpcie.c301 reg = regmap_read_4(rm, stg_base + STG_RP_NEP); in stfpcie_attach()
305 reg = regmap_read_4(rm, stg_base + STG_AWFUN); in stfpcie_attach()
310 reg = regmap_read_4(rm, stg_base + STG_AWFUN); in stfpcie_attach()
395 reg = regmap_read_4(rm, stg_base + STG_ARFUN); in stfpcie_attach()
399 reg = regmap_read_4(rm, stg_base + STG_AWFUN); in stfpcie_attach()
408 reg = regmap_read_4(rm, stg_base + STG_ARFUN); in stfpcie_attach()
411 reg = regmap_read_4(rm, stg_base + STG_AWFUN); in stfpcie_attach()
472 reg = regmap_read_4(rm, stg_base + STG_LNKSTA); in stfpcie_attach()
/openbsd/src/sys/dev/fdt/
Drkpciephy.c147 stat = regmap_read_4(rm, GRF_PCIE30PHY_STATUS0); in rk3568_pciephy_enable()
221 stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY0_STATUS1); in rk3588_pciephy_enable()
227 stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY1_STATUS1); in rk3588_pciephy_enable()
Dimxccm.c519 while ((regmap_read_4(sc->sc_anatop, in imxccm_imx6_enable_pll_enet()
536 while ((regmap_read_4(sc->sc_anatop, in imxccm_imx6_enable_pll_usb1()
553 while ((regmap_read_4(sc->sc_anatop, in imxccm_imx6_enable_pll_usb2()
660 pll0 = regmap_read_4(sc->sc_anatop, in imxccm_imx8mm_get_pll()
662 pll1 = regmap_read_4(sc->sc_anatop, in imxccm_imx8mm_get_pll()
743 regmap_read_4(sc->sc_anatop, pll0) | in imxccm_imx8mm_set_pll()
746 regmap_read_4(sc->sc_anatop, pll0) & in imxccm_imx8mm_set_pll()
754 regmap_read_4(sc->sc_anatop, pll0) | in imxccm_imx8mm_set_pll()
757 reg = regmap_read_4(sc->sc_anatop, pll0); in imxccm_imx8mm_set_pll()
765 regmap_read_4(sc->sc_anatop, pll0) & in imxccm_imx8mm_set_pll()
[all …]
Dsyscon.c152 value = regmap_read_4(rm, sc->sc_offset); in syscon_reset()
170 value = regmap_read_4(rm, sc->sc_offset); in syscon_powerdown()
Damlpwrc.c48 (regmap_read_4((sc)->sc_rm, (reg) << 2))
123 val = regmap_read_4(rm, reg << 2); in amlpwrc_toggle()
Drktcphy.c215 reg = regmap_read_4(sc->sc_grf, GRF_USB3PHY_CON0(sc->sc_phy_ctrl_id)); in rktcphy_set_usb2_only()
225 reg = regmap_read_4(sc->sc_grf, GRF_USB3OTG_CON1(sc->sc_phy_ctrl_id)); in rktcphy_set_usb2_only()
Dmvpinctrl.c41 (regmap_read_4((sc)->sc_rm, (reg)))
342 if (regmap_read_4(sc->sc_rm, XTAL) & XTAL_MODE) in a3700_xtal_get_frequency()
Dimxrtc.c40 (regmap_read_4((sc)->sc_rm, (reg)))
Dmvgpio.c38 (regmap_read_4((sc)->sc_rm, (sc)->sc_offset + (reg)))
Drkpcie.c724 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); in rkpcie_phy_poweron()
740 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); in rkpcie_phy_poweron()
756 status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1); in rkpcie_phy_poweron()
Ddwpcie.c1153 reg = regmap_read_4(gpr, IOMUXC_GPR12); in dwpcie_imx8mq_init()
1168 reg = regmap_read_4(gpr, off); in dwpcie_imx8mq_init()
1177 reg = regmap_read_4(gpr, off); in dwpcie_imx8mq_init()
1182 reg = regmap_read_4(gpr, off); in dwpcie_imx8mq_init()
1195 reg = regmap_read_4(gpr, off); in dwpcie_imx8mq_init()
1207 reg = regmap_read_4(gpr, off); in dwpcie_imx8mq_init()
1211 reg = regmap_read_4(gpr, off); in dwpcie_imx8mq_init()
1241 if (regmap_read_4(phy, IMX8MM_PCIE_PHY_CMN_REG75) == in dwpcie_imx8mq_init()
Drkemmcphy.c63 (regmap_read_4((sc)->sc_rm, (sc)->sc_off + (reg)))
Damltemp.c146 sc->sc_calib = regmap_read_4(rm, offset); in amltemp_attachhook()
Drkusbphy.c313 v = regmap_read_4(sc->sc_grf, r->r_offs); in rkusbphy_rd()
Dmvtemp.c193 return regmap_read_4(sc->sc_rm, sc->sc_offs[reg]); in mvtemp_read()
Drkcomphy.c314 stat = regmap_read_4(phy_rm, in rkcomphy_rk3568_enable()
Dmvclock.c241 reg = regmap_read_4(rm, CP110_PM_CLOCK_GATING_CTRL); in cp110_enable()
Damlclock.c107 (regmap_read_4((sc)->sc_rm, (reg) << 2))
Dif_dwqe_fdt.c404 reg = regmap_read_4(rm, offset); in dwqe_setup_jh7110()
/openbsd/src/sys/arch/armv7/imx/
Dimxahci.c154 reg = regmap_read_4(rm, IOMUXC_GPR13); in imxahci_attach()
164 reg = regmap_read_4(rm, IOMUXC_GPR13); in imxahci_attach()
Dimxtemp.c62 regmap_read_4((sc)->sc_rm, (reg))
139 calibration = regmap_read_4(rm, OCOTP_ANA1); in imxtemp_calibration()
/openbsd/src/sys/arch/armv7/exynos/
Dexehci.c236 val = regmap_read_4(sysrm, USB20PHY_CFG); in exehci_setup()
251 val = regmap_read_4(pmurm, offset); in exehci_setup()
/openbsd/src/sys/arch/armv7/xilinx/
Dzqreset.c101 return regmap_read_4(rm, reg); in zynq_slcr_read()
/openbsd/src/sys/dev/ofw/
Dofw_misc.h30 uint32_t regmap_read_4(struct regmap *, bus_size_t);

12