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Searched refs:shamt (Results 1 – 25 of 27) sorted by relevance

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/openbsd/src/gnu/usr.bin/binutils/cpu/
Diq2000.cpu147 (dnf f-shamt "shift amount field" () 10 5)
367 (dnop shamt "shift amount" () h-uint f-shamt)
452 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD)
458 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD)
489 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU)
495 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU)
501 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16)
510 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16)
519 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND)
525 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND)
[all …]
Diq2000m.cpu211 (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
241 (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
247 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
253 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
259 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
265 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
271 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
277 (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
283 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
289 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
[all …]
Diq10.cpu285 (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD)
293 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32)
299 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B)
305 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S)
314 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL)
320 (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE)
326 (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD)
332 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR)
338 (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID)
344 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA)
[all …]
/openbsd/src/gnu/usr.bin/binutils-2.17/cpu/
Diq2000.cpu130 (dnf f-shamt "shift amount field" () 10 5)
350 (dnop shamt "shift amount" () h-uint f-shamt)
435 (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD)
441 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD)
472 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU)
478 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU)
484 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16)
493 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16)
502 (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND)
508 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND)
[all …]
Diq2000m.cpu211 (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
241 (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
247 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
253 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
259 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
265 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
271 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
277 (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
283 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
289 (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
[all …]
Diq10.cpu285 (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD)
293 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32)
299 (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B)
305 (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S)
314 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL)
320 (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE)
326 (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD)
332 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR)
338 (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID)
344 (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA)
[all …]
Dsh64-compact.cpu1462 (sequence ((QI shamt))
1463 (set shamt (and QI rm 31))
1465 (set rn (sll rn shamt))
1466 (if (ne shamt 0)
1467 (set rn (sra rn (sub 32 shamt)))
1494 (sequence ((QI shamt))
1495 (set shamt (and QI rm 31))
1497 (set rn (sll rn shamt))
1498 (if (ne shamt 0)
1499 (set rn (srl rn (sub 32 shamt)))
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVInstrInfoZb.td283 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
284 "$rd, $rs1, $shamt">;
290 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
291 "$rd, $rs1, $shamt">;
293 // Using RVInstIShiftW since it allocates 5 bits instead of 6 to shamt.
298 (ins GPR:$rs1, shfl_uimm:$shamt), opcodestr,
299 "$rd, $rs1, $shamt">;
500 def : InstAlias<"ror $rd, $rs1, $shamt",
501 (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
505 def : InstAlias<"rorw $rd, $rs1, $shamt",
[all …]
DRISCVInstrInfo.td180 // TODO: should ensure invalid shamt is rejected when decoding.
545 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
546 "$rd, $rs1, $shamt">,
573 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
574 "$rd, $rs1, $shamt">,
1041 def : InstAlias<"sll $rd, $rs1, $shamt",
1042 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1043 def : InstAlias<"srl $rd, $rs1, $shamt",
1044 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1045 def : InstAlias<"sra $rd, $rs1, $shamt",
[all …]
DRISCVInstrFormats.td364 bits<6> shamt;
370 let Inst{25-20} = shamt;
380 bits<5> shamt;
385 let Inst{24-20} = shamt;
DRISCVInstrInfoC.td27 // TODO: should ensure invalid shamt is rejected when decoding.
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86InstrShiftRotate.td857 (ins GR32:$src1, u8imm:$shamt), "",
858 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>;
860 (ins GR64:$src1, u8imm:$shamt), "",
861 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
864 (ins GR32:$src1, u8imm:$shamt), "",
865 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>;
867 (ins GR64:$src1, u8imm:$shamt), "",
868 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>;
872 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
877 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
[all …]
/openbsd/src/sys/arch/mips64/include/
Dmips_opcode.h69 unsigned shamt: 5; member
108 unsigned shamt: 5; member
/openbsd/src/sys/arch/mips64/mips64/
Ddb_disasm.c600 if (i.RType.shamt != 0) in dbmd_print_insn()
604 if (i.RType.shamt != 0) in dbmd_print_insn()
608 if (i.RType.shamt != 0) in dbmd_print_insn()
616 if (i.RType.shamt != 0) in dbmd_print_insn()
637 i.RType.shamt); in dbmd_print_insn()
Dtrap.c685 inst.RType.shamt == 0 && in itsa()
Dfp_emulate.c1846 if ((inst.RType.rt & 0x02) != 0 || inst.RType.shamt != 0) in nofpu_emulate_movci()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsInstrFormats.td18 // shamt - only used on shift instructions, contains the shift amount.
148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
158 bits<5> shamt;
167 let Inst{10-6} = shamt;
247 bits<5> shamt;
256 let Inst{10-6} = shamt;
DMicroMipsInstrFormats.td98 bits<3> shamt;
105 let Inst{3-1} = shamt;
365 bits<5> shamt;
372 let Inst{15-11} = shamt;
DMicroMipsInstrInfo.td336 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
337 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
793 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
1380 def : MipsInstAlias<"sll $rd, $shamt",
1381 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1382 def : MipsInstAlias<"sra $rd, $shamt",
1383 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1384 def : MipsInstAlias<"srl $rd, $shamt",
1385 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
DMicroMips32r6InstrFormats.td530 bits<5> shamt;
537 let Inst{15-11} = shamt;
DMipsDSPInstrInfo.td1372 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
DMips64InstrInfo.td17 // shamt must fit in 6 bits.
414 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
DMipsInstrInfo.td1251 // shamt field must fit in 5 bits.
1363 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
1364 !strconcat(opstr, "\t$rd, $rt, $shamt"),
1365 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsicsRISCV.td67 // ptr addr, ixlen oparg, ixlen mask, ixlen shamt, ixlenimm ordering)
/openbsd/src/gnu/usr.bin/binutils/gas/config/
Dtc-mips.c11550 int treg, sreg, dreg, shamt;
11564 shamt = (oc >> 6) & 0x1f;
11617 printf ("$%d", shamt);

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