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/openbsd/src/gnu/llvm/clang/lib/Headers/
Damxintrin.h153 #define _tile_dpbssd(dst, src0, src1) \ argument
154 __builtin_ia32_tdpbssd((dst), (src0), (src1))
172 #define _tile_dpbsud(dst, src0, src1) \ argument
173 __builtin_ia32_tdpbsud((dst), (src0), (src1))
191 #define _tile_dpbusd(dst, src0, src1) \ argument
192 __builtin_ia32_tdpbusd((dst), (src0), (src1))
210 #define _tile_dpbuud(dst, src0, src1) \ argument
211 __builtin_ia32_tdpbuud((dst), (src0), (src1))
228 #define _tile_dpbf16ps(dst, src0, src1) \ argument
229 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td185 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
188 // out = (src1 > src0) ? 1 : 0
224 // Special case divide FMA with scale and flags (src0 = Quotient,
230 // Special case divide fixup and flags(src0 = Quotient, src1 =
249 // src0: vec4(src, 0, 0, mask)
325 // i32 or f32 src0
385 def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
386 [(int_amdgcn_ldexp node:$src0, node:$src1),
387 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
389 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
[all …]
DAMDGPUInstructions.td165 (ops node:$src0),
166 (op $src0),
175 (ops node:$src0, node:$src1),
176 (op $src0, $src1),
184 (ops node:$src0, node:$src1, node:$src2),
185 (op $src0, $src1, $src2),
193 (ops node:$src0, node:$src1),
194 (op $src0, $src1),
251 def csh_mask_16 : PatFrag<(ops node:$src0), (and node:$src0, imm),
256 def csh_mask_32 : PatFrag<(ops node:$src0), (and node:$src0, imm),
[all …]
DSIInstructions.td71 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
76 (ins VGPR_32:$src0, VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
78 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
81 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
110 (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
119 (ins VSrc_b64:$src0)> {
136 (ins i64imm:$src0)> {
147 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
151 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
155 // the instruction that defines $src0 (which is run in Whole Wave Mode) doesn't
[all …]
DSOPInstructions.td77 bits<8> src0;
79 let Inst{7-0} = !if(ps.has_src0, src0, ?);
87 !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in),
88 (ins SSrc_b32:$src0)),
89 "$sdst, $src0", pattern> {
95 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
96 "$sdst, $src0", pattern>;
100 opName, (outs), (ins SSrc_b32:$src0),
101 "$src0", pattern> {
107 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
[all …]
DEvergreenInstructions.td348 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
366 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
371 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
412 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
464 (fcopysign f32:$src0, f32:$src1),
465 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1)
469 (fcopysign f32:$src0, f64:$src1),
470 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0,
475 (fcopysign f64:$src0, f64:$src1),
477 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
[all …]
DVOPInstructions.td204 bits<9> src0;
217 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
282 // NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
288 let Inst{8} = 0; // No modifiers for src0
298 let Inst{49-41} = src0;
311 let Inst{49-41} = src0;
321 bits<9> src0;
332 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
344 bits<9> src0;
352 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
[all …]
DR600Instructions.td105 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
110 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
136 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
147 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
153 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
175 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
187 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
193 "$src0_neg$src0$src0_rel, "
372 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
373 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
[all …]
DVOP2Instructions.td15 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
27 bits<9> src0;
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
127 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
128 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
130 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
271 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
334 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
342 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, clampmod:$clamp),
[all …]
DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
37 : EXPCommon<0, done, "exp$tgt $src0, $src1, $src2, $src3"
45 : EXPCommon<row, done, "exp$tgt $src0, $src1, $src2, $src3"
130 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
133 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
139 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
142 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
148 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
150 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
DVOP3Instructions.td38 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
63 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
71 let Ins64 = (ins InterpSlot:$src0,
75 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
92 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
96 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
101 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
164 // result = src0 * src1 + src2
171 // result = src0 * src1 + src2
332 (VOP3Mods f32:$src0, i32:$src0_modifiers),
[all …]
DVINTERPInstructions.td16 bits<9> src0;
36 let Inst{40-32} = src0;
71 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
89 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
124 (VINTERPMods f32:$src0, i32:$src0_modifiers),
127 (inst $src0_modifiers, $src0,
143 (pat[0] f32:$src0, i32:$src0_modifiers),
147 (inst $src0_modifiers, $src0,
/openbsd/src/gnu/llvm/llvm/docs/AMDGPU/
DAMDGPUAsmGFX7.rst726 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
727 …nid_gfx7_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx7_vcc>`, :ref:`src0<amdgpu_synid_gfx7_s…
728 …nid_gfx7_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx7_vcc>`, :ref:`src0<amdgpu_synid_gfx7_s…
729 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
730 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
731 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
732 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
733 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
734 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
735 … :ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx7_s…
[all …]
DAMDGPUAsmGFX90a.rst971 …pu_synid_gfx90a_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a…
973 …pu_synid_gfx90a_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx90a_vcc>`, :ref:`src0<amdgpu_synid_gfx90a…
974 …v_add_f16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
976 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
977 …v_add_f32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
979 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
980 …v_add_u16 :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
982 …v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
983 …v_add_u32 :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
985 …v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx90a_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
[all …]
DAMDGPUAsmGFX9.rst1061 …amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_s…
1063 …amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx9_vcc>`, :ref:`src0<amdgpu_synid_gfx9_s…
1064 …v_add_f16 :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1066 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1067 …v_add_f32 :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1069 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1070 …v_add_u16 :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1072 …v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1073 …v_add_u32 :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
1075 …v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
[all …]
DAMDGPUAsmGFX940.rst967 …pu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940…
969 …pu_synid_gfx940_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx940_vcc>`, :ref:`src0<amdgpu_synid_gfx940…
970 …v_add_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
972 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
973 …v_add_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
975 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
976 …v_add_u16 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
978 …v_add_u16_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
979 …v_add_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
981 …v_add_u32_sdwa :ref:`vdst<amdgpu_synid_gfx940_vdst_89680f>`, :ref:`src0<amdgpu_synid_…
[all …]
DAMDGPUAsmGFX1030.rst765 …d_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`src0<amdgpu_synid_gfx103…
766 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdg…
767 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdg…
768 …v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdg…
769 …v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdg…
770 …v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`src0<amdg…
774 …v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3cd7ad>`, :ref:`src0<amdg…
775 …v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3cd7ad>`, :ref:`src0<amdg…
776 …v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3cd7ad>`, :ref:`src0<amdg…
777 …v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx1030_sdst_3cd7ad>`, :ref:`src0<amdg…
[all …]
DAMDGPUAsmGFX10.rst785 …synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_…
786 …v_add_f16_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu…
787 …v_add_f32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu…
788 …v_add_nc_u32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu…
789 …v_and_b32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu…
790 …v_ashrrev_i32_sdwa :ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`src0<amdgpu…
794 …v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu…
795 …v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu…
796 …v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu…
797 …v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid_gfx10_sdst_3759f6>`, :ref:`src0<amdgpu…
[all …]
DAMDGPUAsmGFX8.rst873 …v_add_f16 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
876 …v_add_f32 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
879 …v_add_u16 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
882 …amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx8_vcc>`, :ref:`src0<amdgpu_synid_gfx8_s…
885 …amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx8_vcc>`, :ref:`src0<amdgpu_synid_gfx8_s…
888 …v_and_b32 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
891 …v_ashrrev_i16 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
894 …v_ashrrev_i32 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
897 …v_cndmask_b32 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
900 …v_ldexp_f16 :ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
[all …]
DAMDGPUAsmGFX906.rst43 …v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
45 …v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
47 …v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
56 …v_fmac_f32_e64 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
57 …v_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
66 …v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_sr…
67 …v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_sr…
68 …v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_sr…
69 …v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_sr…
70 …v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_sr…
[all …]
DAMDGPUAsmGFX908.rst63 …v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
65 …v_dot2c_i32_i16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
67 …v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
69 …v_dot8c_i32_i4 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
71 …v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
73 …v_pk_fmac_f16 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
74 …v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
76 …v_xnor_b32_sdwa :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gf…
85 …v_dot2c_f32_f16_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu…
86 …v_dot2c_i32_i16_e64 :ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu…
[all …]
DAMDGPUAsmGFX1011.rst63 …v_dot2c_f32_f16 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
64 …v_dot4c_i32_i8 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
73 …v_dot2_f32_f16 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
74 …v_dot2_i32_i16 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
75 …v_dot2_u32_u16 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
76 …v_dot4_i32_i8 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
77 …v_dot4_u32_u8 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
78 …v_dot8_i32_i4 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
79 …v_dot8_u32_u4 :ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid…
DAMDGPUAsmGFX11.rst1308 …d_gfx11_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx11_vcc>`, :ref:`src0<amdgpu_synid_gfx11_…
1309 … :ref:`vdst<amdgpu_synid_gfx11_vdst_d180f4>`, :ref:`src0<amdgpu_synid_gfx11_…
1310 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1311 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1312 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1313 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1314 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1315 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1316 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
1317 … :ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx11_…
[all …]
/openbsd/src/gnu/usr.bin/gcc/gcc/
Dssa-ccp.c463 rtx src0 = XEXP (src, 0); local
468 if ((GET_CODE (src0) == REG
469 && values[REGNO (src0)].lattice_val == UNDEFINED)
479 mode = GET_MODE (src0);
485 if (GET_CODE (src0) == REG
486 && values[REGNO (src0)].lattice_val == CONSTANT)
487 src0 = values[REGNO (src0)].const_value;
496 mode, src0, src1);
503 rtx src0 = XEXP (src, 0); local
504 enum machine_mode mode0 = GET_MODE (src0);
[all …]
/openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/
Dbfin-dis.c471 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf) in decode_multfunc() argument
476 s0 = dregs_hi (src0); in decode_multfunc()
478 s0 = dregs_lo (src0); in decode_multfunc()
492 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf) in decode_macfunc() argument
520 decode_multfunc (h0, h1, src0, src1, outf); in decode_macfunc()
1434 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask); in decode_COMP3op_0() local
1437 if (opc == 5 && src1 == src0) in decode_COMP3op_0()
1441 OUTS (outf, pregs (src0)); in decode_COMP3op_0()
1448 OUTS (outf, dregs (src0)); in decode_COMP3op_0()
1456 OUTS (outf, dregs (src0)); in decode_COMP3op_0()
[all …]

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