| /openbsd/src/sys/dev/pci/drm/i915/display/ |
| D | intel_dkl_phy_regs.h | 29 #define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ argument
39 #define _DKL_REG(tc_port, phy_offset) \ argument
41 .reg = _DKL_REG_PHY_BASE(tc_port) + \
46 #define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ argument
47 _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))
51 #define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ argument
57 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ argument
76 #define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ argument
84 #define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ argument
95 #define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ argument
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| D | intel_mg_phy_regs.h | 11 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ argument
12 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
18 #define MG_TX1_LINK_PARAMS(ln, tc_port) \ argument
19 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
27 #define MG_TX2_LINK_PARAMS(ln, tc_port) \ argument
28 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
37 #define MG_TX1_PISO_READLOAD(ln, tc_port) \ argument
38 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
46 #define MG_TX2_PISO_READLOAD(ln, tc_port) \ argument
47 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
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| D | intel_dkl_phy.c | 25 enum tc_port tc_port = DKL_REG_TC_PORT(reg); in dkl_phy_set_hip_idx() local
27 drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
30 HIP_INDEX_REG(tc_port), in dkl_phy_set_hip_idx()
31 HIP_INDEX_VAL(tc_port, reg.bank_idx)); in dkl_phy_set_hip_idx()
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| D | intel_dpll_mgr.c | 190 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) in icl_pll_id_to_tc_port()
195 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id() argument
197 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id()
218 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in intel_tc_pll_enable_reg() local
221 return ADLP_PORTTC_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
223 return MG_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
3541 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local
3558 MG_REFCLKIN_CTL(tc_port)); in mg_pll_get_hw_state()
3562 intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); in mg_pll_get_hw_state()
3567 intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); in mg_pll_get_hw_state()
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| D | intel_ddi.c | 1236 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_mg_phy_set_signal_levels() local
1248 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1250 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1260 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1266 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1277 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1286 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
1302 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), in icl_mg_phy_set_signal_levels()
1309 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), in icl_mg_phy_set_signal_levels()
1316 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), in icl_mg_phy_set_signal_levels()
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| D | intel_tc.c | 253 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_port_power_domain() local
255 return POWER_DOMAIN_PORT_DDI_LANES_TC1 + tc_port - TC_PORT_1; in tc_port_power_domain()
300 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in lnl_tc_port_get_max_lane_count() local
305 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in lnl_tc_port_get_max_lane_count()
458 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_phy_load_fia_params() local
465 tc->phy_fia = tc_port / 2; in tc_phy_load_fia_params()
466 tc->phy_fia_idx = tc_port % 2; in tc_phy_load_fia_params()
469 tc->phy_fia_idx = tc_port; in tc_phy_load_fia_params()
810 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in adlp_tc_phy_is_ready() local
815 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adlp_tc_phy_is_ready()
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| D | intel_dpll_mgr.h | 44 enum tc_port;
443 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
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| D | intel_display.h | 155 enum tc_port { enum
466 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
473 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
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| D | intel_display_power_well.c | 533 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
535 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); in icl_tc_phy_aux_power_well_enable()
537 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & in icl_tc_phy_aux_power_well_enable()
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| D | intel_display.c | 1968 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) in intel_port_to_tc()
2007 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) in intel_encoder_to_tc()
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| /openbsd/src/sys/dev/pci/drm/i915/ |
| D | i915_reg.h | 4161 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ argument
4162 (tc_port) + 12 : \
4163 (tc_port) - TC_PORT_4 + 21))
4238 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ argument
4250 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ argument
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