| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 71 MI.tieOperands(0, 1); in tieOpsIfNeeded()
366 MI.tieOperands(0, 1); in processBlock()
|
| D | SystemZPostRewrite.cpp | 217 MI.tieOperands(0, 1); in selectMI()
|
| D | SystemZInstrInfo.cpp | 173 MI.tieOperands(0, 1); in expandRIEPseudo()
669 UseMI.tieOperands(0, 1); in FoldImmediate()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 370 MI.tieOperands( in shrinkMIMG()
541 MI.tieOperands(0, 2); in shrinkScalarLogicOp()
842 MI.tieOperands(0, 1); in runOnMachineFunction()
|
| D | SIPeepholeSDWA.cpp | 486 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
1117 SDWAInst->tieOperands(PreserveDstIdx, SDWAInst->getNumOperands() - 1); in convertToSDWA()
|
| D | SIInstrInfo.cpp | 925 MIB->tieOperands(0, MIB->getNumOperands() - 1); in copyPhysReg()
2120 MIB->tieOperands(ImpDefIdx, ImpUseIdx); in expandPostRAPseudo()
2159 MIB->tieOperands(ImpDefIdx, ImpUseIdx); in expandPostRAPseudo()
5515 Inst.tieOperands(NewVDst, NewVDstIn); in moveFlatAddrToVGPR()
|
| D | AMDGPUInstructionSelector.cpp | 1994 MIB->tieOperands(0, MIB->getNumOperands() - 1); in selectImageIntrinsic()
2204 MovSDWA->tieOperands(0, MovSDWA->getNumOperands() - 1); in selectG_TRUNC()
|
| D | SIRegisterInfo.cpp | 2247 MI->tieOperands(NewVDst, NewVDstIn); in eliminateFrameIndex()
|
| D | SIISelLowering.cpp | 12099 MI.tieOperands(DstIdx, MI.getNumOperands() - 1); in AddIMGInit()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | FixupStatepointCallerSaved.cpp | 533 MIB->tieOperands(NewIndices[OldDef], MIB->getNumOperands() - 1); in rewriteStatepoint()
|
| D | MachineInstr.cpp | 267 tieOperands(DefIdx, OpNo); in addOperand()
1107 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() function in MachineInstr
|
| D | TargetInstrInfo.cpp | 550 NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1); in foldPatchpoint()
|
| D | InlineSpiller.cpp | 905 MI->tieOperands(Tied.first, Tied.second); in foldMemoryOperand()
|
| D | TargetLoweringBase.cpp | 1207 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); in emitPatchPoint()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| D | InlineAsmLowering.cpp | 475 Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1); in lowerInlineAsm()
|
| D | Utils.cpp | 192 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 1179 MI->tieOperands(Def++, Use); in EmitMachineNode()
1346 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 532 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ExpandPseudo.cpp | 585 MI.tieOperands(0, 1); in ExpandMI()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 783 MI.tieOperands(1, 3); in createScratchRegisterForInstruction()
|
| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 1563 void tieOperands(unsigned DefIdx, unsigned UseIdx);
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 523 DefI->tieOperands(DefIdx, DefI->getNumOperands()-1); in updateDeadsInRange()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 1702 MI.tieOperands(TiedPair.first, TiedPair.second); in assignRegisterTies()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2406 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
|
| D | ARMISelLowering.cpp | 12278 MI.tieOperands(DefIdx, i); in AdjustInstrPostInstrSelection()
|