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Searched refs:v32i1 (Results 1 – 14 of 14) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86InstrVecCompiler.td188 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
194 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
197 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
200 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
252 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
255 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
312 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
320 (v32i1 VK32:$mask), (iPTR 0))),
325 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
337 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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DX86CallingConv.td91 // Promote v8i1/v16i1/v32i1 arguments to i32.
92 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
168 // Promote v32i1 arguments to i32.
169 CCIfType<[v32i1], CCPromoteToType<i32>>,
237 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
563 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
878 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86TargetTransformInfo.cpp2096 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, in getCastInstrCost()
2097 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, in getCastInstrCost()
2115 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, in getCastInstrCost()
2116 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, in getCastInstrCost()
2133 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, in getCastInstrCost()
2134 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, in getCastInstrCost()
2342 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, in getCastInstrCost()
2343 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, in getCastInstrCost()
2361 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, in getCastInstrCost()
2362 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, in getCastInstrCost()
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DX86RegisterInfo.td615 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
633 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
DX86InstrAVX512.td188 def v32i1_info : X86KVectorVTInfo<VK32, VK32WM, v32i1>;
2896 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2937 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))),
2939 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))),
2988 defm : operation_gpr_mask_copy_lowering<VK32, v32i1>;
3362 defm D : avx512_mask_setop<VK32, v32i1, Val>;
3394 defm : operation_subvector_mask_lowering<VK1, v1i1, VK32, v32i1>;
3400 defm : operation_subvector_mask_lowering<VK2, v2i1, VK32, v32i1>;
3405 defm : operation_subvector_mask_lowering<VK4, v4i1, VK32, v32i1>;
3409 defm : operation_subvector_mask_lowering<VK8, v8i1, VK32, v32i1>;
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DX86ISelLowering.cpp1386 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom); in X86TargetLowering()
1995 addRegisterClass(MVT::v32i1, &X86::VK32RegClass); in X86TargetLowering()
1998 for (auto VT : { MVT::v32i1, MVT::v64i1 }) { in X86TargetLowering()
2011 for (auto VT : { MVT::v16i1, MVT::v32i1 }) in X86TargetLowering()
2120 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v32i1, MVT::v32i16); in X86TargetLowering()
2121 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v32i1, in X86TargetLowering()
2123 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v32i1, MVT::v32i16); in X86TargetLowering()
2124 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v32i1, in X86TargetLowering()
2134 setOperationAction(ISD::STRICT_FSETCC, MVT::v32i1, Custom); in X86TargetLowering()
2135 setOperationAction(ISD::STRICT_FSETCCS, MVT::v32i1, Custom); in X86TargetLowering()
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DX86InstrCompiler.td618 defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>;
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h71 v32i1 = 22, // 32 x i1 enumerator
411 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 || in is32BitVector()
552 case v32i1: in getVectorElementType()
772 case v32i1: in getVectorMinNumElements()
966 case v32i1: in getSizeInBits()
1274 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td501 [v32i1, v64i1, v32i1]>;
503 [v16i1, v32i1, v16i1]>;
DHexagonISelLoweringHVX.cpp73 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
82 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DValueTypes.td44 def v32i1 : ValueType<32, 22>; // 32 x i1 vector value
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DValueTypes.cpp223 case MVT::v32i1: in getTypeForEVT()
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenTarget.cpp88 case MVT::v32i1: return "MVT::v32i1"; in getEnumName()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsics.td278 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1