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Searched refs:v4f64 (Results 1 – 25 of 28) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp896 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
898 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
900 { ISD::FMUL, MVT::v4f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
906 { ISD::FDIV, MVT::v4f64, { 8, 14, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1092 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd in getArithmeticInstrCost()
1099 { ISD::FADD, MVT::v4f64, { 1, 4, 1, 2 } }, // vaddpd in getArithmeticInstrCost()
1106 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd in getArithmeticInstrCost()
1113 { ISD::FMUL, MVT::v4f64, { 1, 5, 1, 2 } }, // vmulpd in getArithmeticInstrCost()
1121 { ISD::FDIV, MVT::v4f64, { 28, 35, 1, 3 } }, // vdivpd in getArithmeticInstrCost()
1192 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
DX86InstrFMA.td142 v4f64, SchedWriteFMA>, VEX_W;
145 v4f64, SchedWriteFMA>, VEX_W;
148 v2f64, v4f64, SchedWriteFMA>, VEX_W;
151 v2f64, v4f64, SchedWriteFMA>, VEX_W;
163 loadv4f64, X86any_Fnmadd, v2f64, v4f64, SchedWriteFMA>, VEX_W;
165 loadv4f64, X86any_Fnmsub, v2f64, v4f64, SchedWriteFMA>, VEX_W;
583 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", any_fma, v2f64, v4f64,
585 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86any_Fmsub, v2f64, v4f64,
587 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86any_Fnmadd, v2f64, v4f64,
589 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86any_Fnmsub, v2f64, v4f64,
[all …]
DX86CallingConv.td122 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
198 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
249 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
310 CCIfType<[v8f32, v4f64, v8i32, v4i64],
576 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
598 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
653 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>,
717 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
776 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64],
[all …]
DX86InstrVecCompiler.td82 defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>;
106 defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>;
125 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, sub_xmm>;
134 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, sub_xmm>;
148 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, sub_ymm>;
164 defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, sub_ymm>;
DX86InstrSSE.td166 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
294 def : Pat<(v4f64 (X86vzload64 addr:$src)),
425 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>,
433 [(store (v4f64 VR256:$src), addr:$dst)]>,
1586 (v4i32 (X86cvtp2Int (v4f64 VR256:$src))))]>,
1670 (v4i32 (X86any_cvttp2si (v4f64 VR256:$src))))]>,
1685 def : Pat<(v4i32 (any_fp_to_sint (v4f64 VR256:$src))),
1715 [(set VR256:$dst, (v4f64 (any_fpextend (v4f32 VR128:$src))))]>,
1719 [(set VR256:$dst, (v4f64 (extloadv4f32 addr:$src)))]>,
1753 (v4f64 (any_sint_to_fp (loadv4i32 addr:$src))))]>,
[all …]
DX86ISelLowering.cpp897 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) { in X86TargetLowering()
1332 addRegisterClass(MVT::v4f64, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1335 for (auto VT : { MVT::v8f32, MVT::v4f64 }) { in X86TargetLowering()
1370 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Custom); in X86TargetLowering()
1371 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v4f64, Custom); in X86TargetLowering()
1375 setOperationAction(ISD::STRICT_FADD, MVT::v4f64, Legal); in X86TargetLowering()
1377 setOperationAction(ISD::STRICT_FSUB, MVT::v4f64, Legal); in X86TargetLowering()
1379 setOperationAction(ISD::STRICT_FMUL, MVT::v4f64, Legal); in X86TargetLowering()
1381 setOperationAction(ISD::STRICT_FDIV, MVT::v4f64, Legal); in X86TargetLowering()
1383 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f64, Legal); in X86TargetLowering()
[all …]
DX86InstrFragmentsSIMD.td841 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
907 (v4f64 (alignedload node:$ptr))>;
970 def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>;
DX86RegisterInfo.td571 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],
606 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64],
DX86InstrXOP.td461 v4f64, loadv4f64, loadv4i64,
DX86InstrAVX512.td530 def : Pat<(v4f64 immAllZerosV), (AVX512_256_SET0)>;
1012 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
1045 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
1604 def : Pat<(v4f64 (X86SubVBroadcastld128 addr:$src)),
1621 (bc_v8f32 (v4f64 (X86SubVBroadcastld128 addr:$src))),
1625 (bc_v8f32 (v4f64 (X86SubVBroadcastld128 addr:$src))),
1649 (v4f64 immAllZerosV)),
4695 def : Pat<(v4f64 (X86vzload64 addr:$src)),
4778 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
4781 (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))),
[all …]
DX86FastISel.cpp411 case MVT::v4f64: in X86FastEmitLoad()
584 case MVT::v4f64: in X86FastEmitStore()
DX86InstrCompiler.td645 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
672 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h192 v4f64 = 128, // 4 x f64 enumerator
438 SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 || in is256BitVector()
707 case v4f64: in getVectorElementType()
845 case v4f64: in getVectorMinNumElements()
1046 case v4f64: return TypeSize::Fixed(256); in getSizeInBits()
1402 if (NumElements == 4) return MVT::v4f64; in getVectorVT()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVTargetTransformInfo.cpp381 {Intrinsic::floor, MVT::v4f64, 9},
398 {Intrinsic::ceil, MVT::v4f64, 9},
415 {Intrinsic::trunc, MVT::v4f64, 7},
432 {Intrinsic::round, MVT::v4f64, 9},
449 {Intrinsic::roundeven, MVT::v4f64, 9},
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIInstructions.td1555 def : BitConvert <v4i64, v4f64, VReg_256>;
1556 def : BitConvert <v4f64, v4i64, VReg_256>;
1559 def : BitConvert <v4f64, v8i32, VReg_256>;
1560 def : BitConvert <v4f64, v8f32, VReg_256>;
1563 def : BitConvert <v8i32, v4f64, VReg_256>;
1564 def : BitConvert <v8f32, v4f64, VReg_256>;
1579 def : BitConvert <v16f16, v4f64, VReg_256>;
1580 def : BitConvert <v16i16, v4f64, VReg_256>;
1583 def : BitConvert <v4f64, v16f16, VReg_256>;
1584 def : BitConvert <v4f64, v16i16, VReg_256>;
DAMDGPUISelLowering.cpp126 setOperationAction(ISD::LOAD, MVT::v4f64, Promote); in AMDGPUTargetLowering()
127 AddPromotedToType(ISD::LOAD, MVT::v4f64, MVT::v8i32); in AMDGPUTargetLowering()
177 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in AMDGPUTargetLowering()
185 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
252 setOperationAction(ISD::STORE, MVT::v4f64, Promote); in AMDGPUTargetLowering()
253 AddPromotedToType(ISD::STORE, MVT::v4f64, MVT::v8i32); in AMDGPUTargetLowering()
300 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand); in AMDGPUTargetLowering()
301 setTruncStoreAction(MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
351 MVT::v2f64, MVT::v3f64, MVT::v4f64, MVT::v8f64, MVT::v16f64}, in AMDGPUTargetLowering()
373 MVT::v3i64, MVT::v4f64, MVT::v4i64, MVT::v8f64, MVT::v8i64, in AMDGPUTargetLowering()
DSIRegisterInfo.td893 defm "" : SRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], SGPR_256Regs, TTMP_256Regs>;
946 defm VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64, v16i16, v16f16], (add VGPR_256)>;
979 defm AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>;
DSIInstrInfo.td324 !eq(SrcVT.Value, v4f64.Value));
2724 def VOP_V4F64_F64_F64_V4F64 : VOPProfile <[v4f64, f64, f64, v4f64]>;
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DValueTypes.td161 def v4f64 : ValueType<256, 128>; // 4 x f64 vector value
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DValueTypes.cpp435 case MVT::v4f64: in getTypeForEVT()
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenTarget.cpp194 case MVT::v4f64: return "MVT::v4f64"; in getEnumName()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp1923 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 4 }, in getCastInstrCost()
1924 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 4 }, in getCastInstrCost()
/openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp484 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in NVPTXTargetLowering()
485 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand); in NVPTXTargetLowering()
/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp2536 if (Concat.getValueType() != MVT::v4f64) in performVectorTruncZeroCombine()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsics.td342 def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double

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