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Searched refs:v64i8 (Results 1 – 22 of 22) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp346 { ISD::SHL, MVT::v64i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
347 { ISD::SRL, MVT::v64i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
348 { ISD::SRA, MVT::v64i8, { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
365 { ISD::SHL, MVT::v64i8, { 2, 12, 5, 6 } }, // psllw + pand. in getArithmeticInstrCost()
366 { ISD::SRL, MVT::v64i8, { 2, 12, 5, 6 } }, // psrlw + pand. in getArithmeticInstrCost()
367 { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
516 { ISD::SDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
517 { ISD::SREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
518 { ISD::UDIV, MVT::v64i8, { 14 } }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
519 { ISD::UREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
[all …]
DX86CallingConv.td127 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
157 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
202 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
238 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
255 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
564 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
582 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
602 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64],
656 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
721 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrVecCompiler.td96 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
108 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
146 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, sub_xmm>;
153 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, sub_ymm>;
162 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, sub_xmm>;
169 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, sub_ymm>;
DX86ISelLowering.cpp1663 addRegisterClass(MVT::v64i8, &X86::VR512RegClass); in X86TargetLowering()
1747 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1748 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1749 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1776 setOperationAction(ISD::ADD, MVT::v64i8, HasBWI ? Legal : Custom); in X86TargetLowering()
1777 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom); in X86TargetLowering()
1782 setOperationAction(ISD::MUL, MVT::v64i8, Custom); in X86TargetLowering()
1788 setOperationAction(ISD::MULHS, MVT::v64i8, Custom); in X86TargetLowering()
1789 setOperationAction(ISD::MULHU, MVT::v64i8, Custom); in X86TargetLowering()
1791 setOperationAction(ISD::AVGCEILU, MVT::v64i8, HasBWI ? Legal : Custom); in X86TargetLowering()
[all …]
DX86InstrFragmentsSIMD.td855 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
933 (v64i8 (alignedload node:$ptr))>;
973 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
DX86RegisterInfo.td589 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64],
593 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86InstrAVX512.td486 def : Pat<(v64i8 immAllZerosV), (AVX512_512_SET0)>;
1030 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
1032 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
1063 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
1065 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
1542 def : Pat<(v64i8 (X86SubVBroadcastld256 addr:$src)),
1557 def : Pat<(v64i8 (X86SubVBroadcastld128 addr:$src)),
3811 def : Pat<(alignedstore (v64i8 VR512:$src), addr:$dst),
3821 def : Pat<(store (v64i8 VR512:$src), addr:$dst),
4858 def : Pat<(alignednontemporalstore (v64i8 VR512:$src), addr:$dst),
[all …]
DX86FastISel.cpp453 case MVT::v64i8: in X86FastEmitLoad()
624 case MVT::v64i8: in X86FastEmitStore()
DX86ISelDAGToDAG.cpp986 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) { in PreprocessISelDAG()
1010 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) { in PreprocessISelDAG()
4528 VPTESTM_CASE(v64i8, BZ##SUFFIX) \ in getVPTESTMOpc()
DX86InstrCompiler.td676 def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td115 CCIfType<[v16i32,v32i16,v64i8],
121 CCIfType<[v16i32,v32i16,v64i8],
147 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsicsV60.td34 def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))),
35 (v64i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
43 def : Pat <(v64i8 (bitconvert (v64i1 HvxQR:$src1))),
44 (v64i8 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
DHexagonRegisterInfo.td477 [v64i8, v128i8, v64i8]>;
DHexagonISelLoweringHVX.cpp34 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
98 MVT ByteV = Use64b ? MVT::v64i8 : MVT::v128i8; in initializeHVXLowering()
402 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
DHexagonPatternsHVX.td599 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
977 defm: Saturates<v64i8, v32i16>;
DHexagonISelDAGToDAG.cpp112 case MVT::v64i8: in INITIALIZE_PASS()
502 case MVT::v64i8: in SelectIndexedStore()
DHexagonInstrInfo.cpp2728 case MVT::v64i8: in isValidAutoIncImm()
/openbsd/src/gnu/llvm/llvm/include/llvm/Support/
DMachineValueType.h91 v64i8 = 39, // 64 x i8 enumerator
450 SimpleTy == MVT::v128i4 || SimpleTy == MVT::v64i8 || in is512BitVector()
576 case v64i8: in getVectorElementType()
762 case v64i8: in getVectorMinNumElements()
1067 case v64i8: in getSizeInBits()
1297 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DValueTypes.td64 def v64i8 : ValueType<512, 39>; // 64 x i8 vector value
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DValueTypes.cpp257 case MVT::v64i8: in getTypeForEVT()
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenTarget.cpp105 case MVT::v64i8: return "MVT::v64i8"; in getEnumName()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DIntrinsics.td292 def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8