| /NextBSD/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| HD | AArch64MCCodeEmitter.cpp | 270 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
271 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
274 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12)); in getAddSubImmOpValue()
556 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
557 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
558 return ShiftVal == 8 ? 0 : 1; in getMoveVecShifterOpValue()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64TargetTransformInfo.cpp | 55 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
56 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
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| HD | AArch64FastISel.cpp | 1191 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1197 AArch64_AM::LSL, ShiftVal, SetFlags, WantResult); in emitAddSub()
1211 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1218 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1555 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1562 RHSIsKill, ShiftVal); in emitLogicalOp()
1569 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1575 RHSIsKill, ShiftVal); in emitLogicalOp()
4525 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4554 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
[all …]
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| HD | AArch64ISelDAGToDAG.cpp | 550 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
557 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
558 if (ShiftVal > 4) in SelectArithExtendedRegister()
581 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
737 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
739 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/InstPrinter/ |
| HD | AArch64InstPrinter.cpp | 1021 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1033 if (ShiftVal != 0) in printArithExtend()
1034 O << ", lsl #" << ShiftVal; in printArithExtend()
1039 if (ShiftVal != 0) in printArithExtend()
1040 O << " #" << ShiftVal; in printArithExtend()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUISelDAGToDAG.cpp | 1265 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1272 ShiftVal, WidthVal); in SelectS_BFE()
1286 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1287 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
1293 ShiftVal, WidthVal); in SelectS_BFE()
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| HD | AMDGPUISelLowering.cpp | 2585 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
2587 BitsFrom, ShiftVal); in PerformDAGCombine()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86TargetTransformInfo.cpp | 1008 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
1009 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
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| HD | X86ISelLowering.cpp | 4872 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy); in getVShift() local
4873 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
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| /NextBSD/contrib/llvm/lib/Transforms/Scalar/ |
| HD | ScalarReplAggregates.cpp | 2385 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); in RewriteStoreUserOfWholeAlloca() local
2386 EltVal = Builder.CreateLShr(EltVal, ShiftVal, "sroa.store.elt"); in RewriteStoreUserOfWholeAlloca()
2431 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); in RewriteStoreUserOfWholeAlloca() local
2432 EltVal = Builder.CreateLShr(EltVal, ShiftVal, "sroa.store.elt"); in RewriteStoreUserOfWholeAlloca()
2533 Value *ShiftVal = ConstantInt::get(SrcField->getType(), Shift); in RewriteLoadUserOfWholeAlloca() local
2534 SrcField = BinaryOperator::CreateShl(SrcField, ShiftVal, "", LI); in RewriteLoadUserOfWholeAlloca()
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| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZISelLowering.cpp | 1811 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
1820 ShiftVal = Amount; in isSimpleShift()
1968 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
1971 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
1973 MaskVal >> ShiftVal, in adjustForTestUnderMask()
1974 CmpVal >> ShiftVal, in adjustForTestUnderMask()
1977 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
1980 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
1982 MaskVal << ShiftVal, in adjustForTestUnderMask()
1983 CmpVal << ShiftVal, in adjustForTestUnderMask()
[all …]
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsFastISel.cpp | 1722 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
1738 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
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| /NextBSD/contrib/llvm/tools/clang/lib/CodeGen/ |
| HD | CGBuiltin.cpp | 6224 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue(); in EmitX86BuiltinExpr() local
6234 if (ShiftVal >= (2 * NumLaneElts)) in EmitX86BuiltinExpr()
6239 if (ShiftVal > NumLaneElts) { in EmitX86BuiltinExpr()
6240 ShiftVal -= NumLaneElts; in EmitX86BuiltinExpr()
6249 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
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