| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMExpandPseudoInsts.cpp | 438 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVLD() 491 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVST() 581 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandLaneOp() 682 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm() 683 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm() 731 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm() 732 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm() 944 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI() 959 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI() 1058 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI() [all …]
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| HD | ARMInstrInfo.cpp | 131 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandLoadStackGuard()
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| HD | ARMISelDAGToDAG.cpp | 1917 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1); in SelectVLD() 2037 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1); in SelectVST() 2060 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1); in SelectVST() 2079 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1); in SelectVST() 2184 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1); in SelectVLDSTLane() 2270 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1); in SelectVLDDup() 3095 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1); in Select() 3162 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in Select()
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| HD | Thumb2SizeReduction.cpp | 514 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
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| HD | ARMLoadStoreOptimizer.cpp | 1221 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in MergeBaseUpdateLSMultiple() 1926 MI->setMemRefs(MemBegin, MemEnd); in concatenateMemOperands()
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| HD | ARMBaseInstrInfo.cpp | 1374 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end()); in reMaterialize() 4065 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandLoadStackGuardBase()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonISelDAGToDAG.cpp | 271 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadSignExtend64() 293 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadSignExtend64() 328 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadZeroExtend64() 355 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadZeroExtend64() 422 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoad() 445 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoad() 513 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedStore() 545 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedStore()
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| HD | HexagonExpandCondsets.cpp | 929 MB.setMemRefs(MemRefs, MemRefs+NR); in predicateAt()
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | MachineInstrBuilder.h | 163 const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b, in setMemRefs() function 165 MI->setMemRefs(b, e); in setMemRefs()
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| HD | MachineInstr.h | 1156 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
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| HD | SelectionDAGNodes.h | 2173 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetInstrInfo.cpp | 482 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in foldMemoryOperand() 554 NewMI->setMemRefs(LoadMI->memoperands_begin(), in foldMemoryOperand() 559 NewMI->setMemRefs(MI->memoperands_begin(), in foldMemoryOperand()
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| HD | ImplicitNullChecks.cpp | 300 MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end()); in insertFaultingLoad()
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| HD | MachineInstr.cpp | 839 setMemRefs(NewMemRefs, NewMemRefs + NewNum); in addMemOperand()
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| HD | TargetLoweringBase.cpp | 1138 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in emitPatchPoint()
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsInstrInfo.cpp | 286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); in genInstrWithNewOpc()
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreISelDAGToDAG.cpp | 156 cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1); in Select()
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430ISelDAGToDAG.cpp | 368 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectIndexedBinOp()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXISelDAGToDAG.cpp | 852 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectLoad() 1234 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectLoadVector() 1990 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectLDGLDU() 2221 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStore() 2596 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStoreVector() 2846 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStoreRetval() 3002 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStoreParam()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | ScheduleDAGSDNodes.cpp | 160 MN->setMemRefs(Begin, End); in CloneNodeWithValues()
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| HD | InstrEmitter.cpp | 808 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), in EmitMachineNode()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelDAGToDAG.cpp | 1320 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in SelectStoreLane() 1355 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in SelectPostStoreLane() 2377 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1); in Select() 2397 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in Select()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelDAGToDAG.cpp | 1925 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); in SelectAtomicLoadArith() 2870 Result->setMemRefs(MemOp, MemOp + 2); in Select()
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| HD | X86InstrInfo.cpp | 4104 (*MIB).setMemRefs(MMOBegin, MMOEnd); in storeRegToAddr() 4138 (*MIB).setMemRefs(MMOBegin, MMOEnd); in loadRegFromAddr() 5700 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); in unfoldMemoryOperand() 5744 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second); in unfoldMemoryOperand()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 8358 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjSetJmp() 8374 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjSetJmp() 8409 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjSetJmp() 8476 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp() 8488 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp() 8500 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp() 8512 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp() 8521 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp()
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