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Searched refs:addUse (Results 1 – 25 of 41) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp279 .addUse(TiedDest) in buildUnalignedLoad()
334 .addUse(PseudoMULTuReg); in select()
363 .addUse(Mips::ZERO) in select()
376 .addUse(I.getOperand(2).getReg()) in select()
384 .addUse(I.getOperand(0).getReg()) in select()
385 .addUse(JTIndex); in select()
393 .addUse(DestAddress) in select()
405 .addUse(DestTmp) in select()
406 .addUse(MF.getInfo<MipsFunctionInfo>() in select()
414 .addUse(Dest); in select()
[all …]
DMipsISelLowering.cpp4790 .addUse(Address) in emitLDR_W()
4792 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4802 .addUse(Address) in emitLDR_W()
4804 .addUse(Undef); in emitLDR_W()
4807 .addUse(Address) in emitLDR_W()
4809 .addUse(LoadHalf); in emitLDR_W()
4810 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4837 .addUse(Address) in emitLDR_D()
4839 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4846 .addUse(Address) in emitLDR_D()
[all …]
DMipsSEISelDAGToDAG.cpp135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
DMipsCallLowering.cpp224 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
487 MIB.addUse(CalleeReg); in lowerCall()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64SpeculationHardening.cpp233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
[all …]
DAArch64ExpandPseudoInsts.cpp334 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
335 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
342 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
343 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
346 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
682 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB); in expandSetTagLoop()
824 .addUse(CtxReg) in expandStoreSwiftAsyncContext()
825 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
841 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
846 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
[all …]
DAArch64LowerHomogeneousPrologEpilog.cpp314 .addUse(AArch64::SP) in getOrCreateFrameHelper()
330 .addUse(AArch64::LR) in getOrCreateFrameHelper()
558 .addUse(AArch64::SP) in lowerProlog()
DAArch64FrameLowering.cpp1444 .addUse(AArch64::FP) in emitPrologue()
1445 .addUse(AArch64::X16) in emitPrologue()
1454 .addUse(AArch64::FP) in emitPrologue()
1581 .addUse(HaveInitialContext ? AArch64::X22 : AArch64::XZR) in emitPrologue()
1582 .addUse(AArch64::SP) in emitPrologue()
2064 .addUse(AArch64::FP) in emitEpilogue()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp2123 .addUse(Hi) in extractF64Exponent()
2124 .addUse(Const0.getReg(0)) in extractF64Exponent()
2125 .addUse(Const1.getReg(0)); in extractF64Exponent()
2196 .addUse(CvtHi.getReg(0)) in legalizeITOFP()
2197 .addUse(ThirtyTwo.getReg(0)); in legalizeITOFP()
2217 .addUse(Unmerge.getReg(1)); in legalizeITOFP()
2230 .addUse(FVal.getReg(0)) in legalizeITOFP()
2231 .addUse(Scale.getReg(0)); in legalizeITOFP()
2415 .addUse(MulVal.getReg(0)) in legalizeSinCos()
2423 .addUse(TrigVal) in legalizeSinCos()
[all …]
DAMDGPUPostLegalizerCombiner.cpp230 .addUse(SqrtSrcMI->getOperand(0).getReg()) in matchRcpSqrtToRsq()
240 .addUse(RcpSrcMI->getOperand(0).getReg()) in matchRcpSqrtToRsq()
DSIFormMemoryClauses.cpp392 Kill.addUse(Reg, std::get<0>(Op), std::get<1>(Op)); in runOnMachineFunction()
DAMDGPURegisterBankInfo.cpp659 .addUse(Reg); in split64BitValueForMapping()
1413 .addUse(RSrc) // rsrc in applyMappingSBufferLoad()
1414 .addUse(VIndex) // vindex in applyMappingSBufferLoad()
1415 .addUse(VOffset) // voffset in applyMappingSBufferLoad()
1416 .addUse(SOffset) // soffset in applyMappingSBufferLoad()
1857 .addUse(SrcReg); in buildVCopy()
1867 .addUse(SrcReg, 0, AMDGPU::sub0); in buildVCopy()
1870 .addUse(SrcReg, 0, AMDGPU::sub1); in buildVCopy()
1873 .addUse(TmpReg0) in buildVCopy()
1875 .addUse(TmpReg1) in buildVCopy()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp581 .addUse(LHSReg) in insertComparison()
582 .addUse(RHSReg) in insertComparison()
600 .addUse(PrevRes) in insertComparison()
778 .addUse(CondReg) in selectSelect()
794 .addUse(TrueReg) in selectSelect()
795 .addUse(FalseReg) in selectSelect()
888 .addUse(AndResult) in select()
938 .addUse(SrcReg) in select()
DARMCallLowering.cpp122 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp653 RegSequence.addUse(Regs[I]); in createTuple()
1001 .addUse(SrcReg) in selectCopy()
1866 Shl.addUse(Src2Reg); in selectVectorSHL()
1953 .addUse(ArgsAddrReg) in selectVaStartDarwin()
1954 .addUse(ListReg) in selectVaStartDarwin()
1981 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2693 .addUse(SrcReg, 0, in select()
2759 .addUse(I.getOperand(2).getReg()) in select()
2909 .addUse(NewDst) in select()
2938 IsStore ? NewInst.addUse(CurValReg) : NewInst.addDef(CurValReg); in select()
[all …]
DAArch64LegalizerInfo.cpp1210 NewI.addUse(Base); in legalizeLoadStore()
1398 .addUse(HSum); in legalizeCTPOP()
1455 .addUse(DesiredI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
1457 .addUse(DesiredI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
1460 .addUse(NewI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
1462 .addUse(NewI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
DAArch64CallLowering.cpp286 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
464 MIB.addUse(AArch64::X21, RegState::Implicit); in lowerReturn()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp274 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
283 .addUse(TablePtr) in buildBrJT()
285 .addUse(IndexReg); in buildBrJT()
853 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
854 .addUse(CmpVal) in buildAtomicCmpXchgWithSuccess()
855 .addUse(NewVal) in buildAtomicCmpXchgWithSuccess()
878 .addUse(Addr) in buildAtomicCmpXchg()
879 .addUse(CmpVal) in buildAtomicCmpXchg()
880 .addUse(NewVal) in buildAtomicCmpXchg()
DRegBankSelect.cpp164 .addUse(Src); in repairReg()
196 MergeBuilder.addUse(SrcReg); in repairReg()
205 UnMergeBuilder.addUse(MO.getReg()); in repairReg()
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVEInstrInfo.cpp795 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
796 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
800 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
801 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86CallLowering.cpp110 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
366 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
DX86FrameLowering.cpp1551 .addUse(MachineFramePtr) in emitPrologue()
1552 .addUse(X86::RIP) in emitPrologue()
1554 .addUse(X86::NoRegister) in emitPrologue()
1557 .addUse(X86::NoRegister); in emitPrologue()
1564 .addUse(MachineFramePtr) in emitPrologue()
1733 .addUse(X86::RSP) in emitPrologue()
1735 .addUse(X86::NoRegister) in emitPrologue()
1737 .addUse(X86::NoRegister) in emitPrologue()
1740 .addUse(X86::RSP) in emitPrologue()
2313 .addUse(MachineFramePtr) in emitEpilogue()
/openbsd/src/gnu/llvm/llvm/include/llvm/IR/
DValue.h505 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
868 if (V) V->addUse(*this); in set()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h1072 void addUse(SDUse &U) { U.addToList(&UseList); }
1215 V->addUse(*this);
1220 V->addUse(*this);
1226 if (N) N->addUse(*this);
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h156 MIB.addUse(Reg); in addSrcToMIB()
159 MIB.addUse(SrcMIB->getOperand(0).getReg()); in addSrcToMIB()

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